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https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk
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Rev 8 |
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Line 18... |
out_sof, // Output Start of Frame
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out_sof, // Output Start of Frame
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out_eof, // Output End of Frame
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out_eof, // Output End of Frame
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out_src_rdy, // Output Source Ready
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out_src_rdy, // Output Source Ready
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in_dst_rdy, // Input Destination Ready
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in_dst_rdy, // Input Destination Ready
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usr_clk_out // User clock out
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usr_clk_out, // User clock out
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usr_rst_out // User reset signal
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);
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);
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// Port mode declarations:
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// Port mode declarations:
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// Inputs:
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// Inputs:
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input clk;
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input clk;
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output out_sof;
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output out_sof;
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output out_eof;
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output out_eof;
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output out_src_rdy;
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output out_src_rdy;
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output in_dst_rdy;
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output in_dst_rdy;
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output usr_clk_out;
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output usr_clk_out;
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output usr_rst_out;
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// Control Register Masks
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// Control Register Masks
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`define START 1
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`define START 1
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`define FREERUN 2
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`define FREERUN 2
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reg [7:0] control_reg;
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reg [7:0] control_reg;
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assign in_dst_rdy = 1;
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assign in_dst_rdy = 1;
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assign out_data = 0;
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assign out_data = 0;
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assign out_sof = 0;
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assign out_sof = 0;
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assign out_eof = 0;
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assign out_eof = 0;
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assign out_src_rdy = 0;
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assign out_src_rdy = 0;
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assign usr_rst_out = control_reg[2];
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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