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[/] [fpga-median/] [trunk/] [rtl/] [dff_3_pipe.v] - Diff between revs 2 and 9

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// +----------------------------------------------------------------------------
/* --------------------------------------------------------------------------------
// Universidade Federal da Bahia
 This file is part of FPGA Median Filter.
//------------------------------------------------------------------------------
 
// PROJECT: FPGA Median Filter
    FPGA Median Filter is free software: you can redistribute it and/or modify
//------------------------------------------------------------------------------
    it under the terms of the GNU General Public License as published by
// FILE NAME            : pixel_network.v
    the Free Software Foundation, either version 3 of the License, or
// AUTHOR               : João Carlos Bittencourt
    (at your option) any later version.
// AUTHOR'S E-MAIL      : joaocarlos@ieee.org
 
// -----------------------------------------------------------------------------
    FPGA Median Filter is distributed in the hope that it will be useful,
// RELEASE HISTORY
    but WITHOUT ANY WARRANTY; without even the implied warranty of
// VERSION  DATE        AUTHOR        DESCRIPTION
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// 1.0      2013-08-13  joao.nunes    initial version
    GNU General Public License for more details.
// -----------------------------------------------------------------------------
 
// KEYWORDS: dff, flip-flop, register bank
    You should have received a copy of the GNU General Public License
// -----------------------------------------------------------------------------
    along with FPGA Median Filter.  If not, see <http://www.gnu.org/licenses/>.
// PURPOSE: Group median pipeline registers.
-------------------------------------------------------------------------------- */
// -----------------------------------------------------------------------------
/* +----------------------------------------------------------------------------
 
   Universidade Federal da Bahia
 
  ------------------------------------------------------------------------------
 
   PROJECT: FPGA Median Filter
 
  ------------------------------------------------------------------------------
 
   FILE NAME            : pixel_network.v
 
   AUTHOR               : João Carlos Bittencourt
 
   AUTHOR'S E-MAIL      : joaocarlos@ieee.org
 
   -----------------------------------------------------------------------------
 
   RELEASE HISTORY
 
   VERSION  DATE        AUTHOR        DESCRIPTION
 
   1.0      2013-08-13  joao.nunes    initial version
 
   -----------------------------------------------------------------------------
 
   KEYWORDS: dff, flip-flop, register bank
 
   -----------------------------------------------------------------------------
 
   PURPOSE: Group median pipeline registers.
 
   ----------------------------------------------------------------------------- */
module dff_3_pipe
module dff_3_pipe
#(
#(
    parameter DATA_WIDTH = 8
    parameter DATA_WIDTH = 8
)(
)(
    input clk,
    input clk,

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