| Line 33... |
Line 33... |
/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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module post_norm( clk, fpu_op, sign, rmode, fract_in, exp_in, exp_ovf,
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module post_norm( clk, fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf,
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opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out,
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opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out,
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ine, overflow, underflow);
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ine, overflow, underflow, f2i_out_sign);
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input clk;
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input clk;
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input [2:0] fpu_op;
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input [2:0] fpu_op;
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input opas;
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input sign;
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input sign;
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input [1:0] rmode;
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input [1:0] rmode;
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input [47:0] fract_in;
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input [47:0] fract_in;
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input [1:0] exp_ovf;
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input [1:0] exp_ovf;
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input [7:0] exp_in;
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input [7:0] exp_in;
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| Line 50... |
Line 51... |
input [4:0] div_opa_ldz;
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input [4:0] div_opa_ldz;
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input output_zero;
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input output_zero;
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output [30:0] out;
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output [30:0] out;
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output ine;
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output ine;
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output overflow, underflow;
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output overflow, underflow;
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output f2i_out_sign;
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires and registers
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// Local Wires and registers
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//
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//
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| Line 70... |
Line 72... |
wire [7:0] exp_out_final;
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wire [7:0] exp_out_final;
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reg [7:0] exp_out_rnd;
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reg [7:0] exp_out_rnd;
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wire op_dn = opa_dn | opb_dn;
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wire op_dn = opa_dn | opb_dn;
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wire op_mul = fpu_op[2:0]==3'b010;
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wire op_mul = fpu_op[2:0]==3'b010;
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wire op_div = fpu_op[2:0]==3'b011;
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wire op_div = fpu_op[2:0]==3'b011;
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wire op_i2f = fpu_op[2:0]==3'b100;
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wire op_f2i = fpu_op[2:0]==3'b101;
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reg [5:0] fi_ldz;
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reg [5:0] fi_ldz;
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wire g, r, s;
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wire g, r, s;
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wire round, round2, round2a, round2_fasu, round2_fmul;
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wire round, round2, round2a, round2_fasu, round2_fmul;
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wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a;
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wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a;
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| Line 119... |
Line 123... |
wire [5:0] fi_ldz_mi22;
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wire [5:0] fi_ldz_mi22;
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wire exp_zero;
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wire exp_zero;
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wire [6:0] ldz_all;
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wire [6:0] ldz_all;
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wire [7:0] ldz_dif;
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wire [7:0] ldz_dif;
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wire [8:0] div_scht1a;
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wire [7:0] f2i_shft;
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wire [55:0] exp_f2i_1;
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wire f2i_zero, f2i_max;
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wire [7:0] f2i_emin;
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wire [7:0] conv_shft;
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wire [7:0] exp_i2f, exp_f2i, conv_exp;
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wire round2_f2i;
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Normalize and Round Logic
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// Normalize and Round Logic
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//
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//
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| Line 187... |
Line 200... |
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wire exp_in_80;
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wire exp_in_80;
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wire rmode_00, rmode_01, rmode_10, rmode_11;
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wire rmode_00, rmode_01, rmode_10, rmode_11;
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// Misc common signals
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// Misc common signals
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assign exp_in_ff = &exp_in;
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assign exp_in_ff = &exp_in;
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assign exp_in_00 = !(|exp_in);
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assign exp_in_00 = !(|exp_in);
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assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
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assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
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assign exp_out_ff = &exp_out;
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assign exp_out_ff = &exp_out;
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assign exp_out_00 = !(|exp_out);
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assign exp_out_00 = !(|exp_out);
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| Line 208... |
Line 220... |
assign rmode_11 = (rmode==2'b11);
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assign rmode_11 = (rmode==2'b11);
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// Fasu Output will be denormalized ...
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// Fasu Output will be denormalized ...
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assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
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assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Fraction Normalization
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// Fraction Normalization
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wire [8:0] div_scht1a;
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parameter f2i_emax = 8'h9d;
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// Incremented fraction for rounding
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assign fract_out_pl1 = fract_out + 1;
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assign fract_out_pl1 = fract_out + 1;
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// Special Signals for f2i
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assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f;
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assign f2i_zero = (!opas & (exp_in<f2i_emin)) | (opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & (fract_in_00 | !rmode_11));
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assign f2i_max = (!opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & !fract_in_00 & rmode_11);
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// Claculate various shifting options
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// Claculate various shifting options
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assign {shft_co,shftr_mul} = (!exp_ovf[1] & exp_in_00) ? {1'b0, exp_out} : exp_in_mi1 ;
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assign {shft_co,shftr_mul} = (!exp_ovf[1] & exp_in_00) ? {1'b0, exp_out} : exp_in_mi1 ;
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assign {div_shft1_co, div_shft1} = exp_in_00 ? {1'b0, div_opa_ldz} : div_scht1a;
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assign {div_shft1_co, div_shft1} = exp_in_00 ? {1'b0, div_opa_ldz} : div_scht1a;
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| Line 228... |
Line 245... |
assign div_shft4 = div_opa_ldz-exp_in;
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assign div_shft4 = div_opa_ldz-exp_in;
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assign div_dn = op_dn & div_shft1_co;
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assign div_dn = op_dn & div_shft1_co;
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assign div_nr = op_dn & exp_ovf[1] & !(|fract_in[46:23]) & (div_shft3>8'h16);
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assign div_nr = op_dn & exp_ovf[1] & !(|fract_in[46:23]) & (div_shft3>8'h16);
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assign f2i_shft = exp_in-8'h7d;
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// Select shifting direction
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// Select shifting direction
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assign left_right = op_div ? lr_div : op_mul ? lr_mul : 1;
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assign left_right = op_div ? lr_div : op_mul ? lr_mul : 1;
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assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1 :
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assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1 :
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| Line 239... |
Line 257... |
(op_dn & div_shft1_co) ? 0 :
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(op_dn & div_shft1_co) ? 0 :
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(op_dn & exp_out_00) ? 1 :
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(op_dn & exp_out_00) ? 1 :
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(!op_dn & exp_out_00 & !exp_ovf[1]) ? 1 :
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(!op_dn & exp_out_00 & !exp_ovf[1]) ? 1 :
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exp_ovf[1] ? 0 :
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exp_ovf[1] ? 0 :
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1;
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1;
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assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) |
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assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) |
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(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1 :
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(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1 :
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( exp_ovf[1] | exp_in_00 ) ? 0 :
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( exp_ovf[1] | exp_in_00 ) ? 0 :
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1;
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1;
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// Select Left and Right shift value
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// Select Left and Right shift value
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assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h2 : exp_in_pl1[7:0]) : {2'h0, fi_ldz};
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assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h2 : exp_in_pl1[7:0]) : {2'h0, fi_ldz};
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assign shift_right = op_div ? shftr_div : shftr_mul;
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assign shift_right = op_div ? shftr_div : shftr_mul;
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assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : fasu_shift;
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assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz};
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assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift;
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assign shftl_mul = (shft_co |
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assign shftl_mul = (shft_co |
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(!exp_ovf[1] & exp_in_00) |
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(!exp_ovf[1] & exp_in_00) |
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(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz};
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(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz};
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assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] :
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assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] :
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(!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] :
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(!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] :
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{2'h0, fi_ldz};
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{2'h0, fi_ldz};
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assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 :
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assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 :
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(op_dn & div_shft1_co) ? div_shft4 :
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(op_dn & div_shft1_co) ? div_shft4 :
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div_shft2;
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div_shft2;
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// Do the actual shifting
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// Do the actual shifting
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assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
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assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
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assign fract_in_shftl = (|shift_left[7:6] ) ? 0 : fract_in<<shift_left[5:0];
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assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<<shift_left[5:0];
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// Chose final fraction output
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// Chose final fraction output
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assign {fract_out,fract_trunc} = left_right ? fract_in_shftl : fract_in_shftr;
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assign {fract_out,fract_trunc} = left_right ? fract_in_shftl : fract_in_shftr;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Exponent Normalization
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// Exponent Normalization
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assign fi_ldz_mi1 = fi_ldz - 1;
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assign fi_ldz_mi1 = fi_ldz - 1;
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assign fi_ldz_mi22 = fi_ldz - 22;
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assign fi_ldz_mi22 = fi_ldz - 22;
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| Line 282... |
Line 299... |
assign exp_in_pl1 = exp_in + 1; // 9 bits - includes carry out
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assign exp_in_pl1 = exp_in + 1; // 9 bits - includes carry out
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assign exp_in_mi1 = exp_in - 1; // 9 bits - includes carry out
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assign exp_in_mi1 = exp_in - 1; // 9 bits - includes carry out
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assign exp_out1_mi1 = exp_out1 - 1;
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assign exp_out1_mi1 = exp_out1 - 1;
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assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
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assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
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assign exp_fix_diva = exp_in - fi_ldz_mi22;
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assign exp_fix_diva = exp_in - fi_ldz_mi22;
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assign exp_fix_divb = exp_in - fi_ldz_mi1;
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assign exp_fix_divb = exp_in - fi_ldz_mi1;
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assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul & (!exp_rnd_adj2a | !rmode[1])) | (op_mul & exp_out1_co);
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assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul & (!exp_rnd_adj2a | !rmode[1])) | (op_mul & exp_out1_co);
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assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
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assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
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assign exp_out = op_div ? exp_div : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
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assign f2i_out_sign = !opas ? ((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 0 : opas) :
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((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 1 : opas);
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assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
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assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
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assign exp_f2i = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
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assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
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assign exp_out = op_div ? exp_div : (op_f2i | op_i2f) ? conv_exp : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
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assign ldz_all = div_opa_ldz + fi_ldz;
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assign ldz_all = div_opa_ldz + fi_ldz;
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assign ldz_dif = fi_ldz_2 - div_opa_ldz;
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assign ldz_dif = fi_ldz_2 - div_opa_ldz;
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assign fi_ldz_2a = 6'd23 - fi_ldz;
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assign fi_ldz_2a = 6'd23 - fi_ldz;
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assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
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assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
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assign div_exp1 = exp_in_mi1 + fi_ldz_2; // 9 bits - includes carry out
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assign div_exp1 = exp_in_mi1 + fi_ldz_2; // 9 bits - includes carry out
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assign div_exp2 = exp_in_pl1 - ldz_all;
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assign div_exp2 = exp_in_pl1 - ldz_all;
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assign div_exp3 = exp_in + ldz_dif;
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assign div_exp3 = exp_in + ldz_dif;
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assign exp_div =(opa_dn & opb_dn) ? div_exp3 :
|
assign exp_div =(opa_dn & opb_dn) ? div_exp3 :
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opb_dn ? div_exp1[7:0] :
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opb_dn ? div_exp1[7:0] :
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| Line 319... |
Line 348... |
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// Round to nearest even
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// Round to nearest even
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assign round = (g & r) | (r & s) ;
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assign round = (g & r) | (r & s) ;
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assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out};
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assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out};
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assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
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assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
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assign ovf0 = exp_out_final_ff & !rmode_01;
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assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i;
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|
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// round to zero
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// round to zero
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assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn) ? 23'h7fffff : fract_out;
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assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out;
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assign exp_fix_div = (fi_ldz>23) ? exp_fix_diva : exp_fix_divb;
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assign exp_fix_div = (fi_ldz>22) ? exp_fix_diva : exp_fix_divb;
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assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) :
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assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) :
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exp_out_ff ? exp_in : exp_out;
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(exp_out_ff & !op_f2i) ? exp_in : exp_out;
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|
|
assign ovf1 = exp_out_ff & !dn;
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assign ovf1 = exp_out_ff & !dn;
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|
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// round to +inf (UP) and -inf (DOWN)
|
// round to +inf (UP) and -inf (DOWN)
|
//assign r_sign = rmode_11 ? !sign : sign;
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|
assign r_sign = sign;
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assign r_sign = sign;
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|
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assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff);
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assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff);
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assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a));
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assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a));
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| Line 349... |
Line 376... |
( exp_ovf[1] & !exp_ovf[0] & exp_out1_co)
|
( exp_ovf[1] & !exp_ovf[0] & exp_out1_co)
|
)
|
)
|
)
|
)
|
);
|
);
|
|
|
assign round2 = (op_mul | op_div) ? round2_fmul : round2_fasu;
|
assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc));
|
|
assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu;
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|
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assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out};
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assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out};
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assign exp_out_rnd2a = exp_rnd_adj2a ? (exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1 : exp_out;
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assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out;
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|
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assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn) ? 23'h7fffff : fract_out_rnd2a;
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assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a;
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assign exp_out_rnd2 = (r_sign & exp_out_ff) ? 8'hfe : exp_out_rnd2a;
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assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a;
|
|
|
|
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// Choose rounding mode
|
// Choose rounding mode
|
always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2)
|
always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2)
|
case(rmode) // synopsys full_case parallel_case
|
case(rmode) // synopsys full_case parallel_case
|
| Line 425... |
Line 453... |
(rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign)
|
(rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign)
|
)
|
)
|
) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 24) & (exp_out_rnd!=8'hfe) );
|
) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 24) & (exp_out_rnd!=8'hfe) );
|
|
|
assign fract_out_final = (inf_out | ovf0 | output_zero) ? 23'h0 :
|
assign fract_out_final = (inf_out | ovf0 | output_zero) ? 23'h0 :
|
max_num ? 23'h7fffff :
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(max_num | (f2i_max & op_f2i) ) ? 23'h7fffff :
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fract_out_rnd;
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fract_out_rnd;
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assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero) ? 8'h00 :
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assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero) ? 8'h00 :
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((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out) ? 8'hff :
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((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff :
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max_num ? 8'hfe :
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max_num ? 8'hfe :
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exp_out_rnd;
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exp_out_rnd;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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| Line 489... |
Line 517... |
(!rmode_00 & max_num) |
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(!rmode_00 & max_num) |
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(exp_in[7] & op_dn & exp_out_ff) |
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(exp_in[7] & op_dn & exp_out_ff) |
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(exp_ovf[0] & (exp_ovf[1] | exp_out_ff) );
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(exp_ovf[0] & (exp_ovf[1] | exp_out_ff) );
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|
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assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1);
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assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1);
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assign ine = (r & !dn) | (s & !dn) | max_num | (op_div & !rem_00);
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|
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wire f2i_ine;
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|
|
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assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) |
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(|fract_trunc) |
|
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(f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) |
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(f2i_max & rmode_11 & (exp_in<8'h80));
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assign ine = op_f2i ? f2i_ine :
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op_i2f ? (|fract_trunc) :
|
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((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00));
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|
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Debugging Stuff
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// Debugging Stuff
|
|
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// synopsys translate_off
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// synopsys translate_off
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| Line 505... |
Line 545... |
wire [7:0] exp_out_del;
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wire [7:0] exp_out_del;
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wire [22:0] fract_out_del;
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wire [22:0] fract_out_del;
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wire [47:0] fract_in_del;
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wire [47:0] fract_in_del;
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wire overflow_del;
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wire overflow_del;
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wire [1:0] exp_ovf_del;
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wire [1:0] exp_ovf_del;
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wire [22:0] fract_out_x_del;
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wire [22:0] fract_out_x_del, fract_out_rnd2a_del;
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wire [24:0] trunc_xx_del;
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wire [24:0] trunc_xx_del;
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wire exp_rnd_adj2a_del;
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wire exp_rnd_adj2a_del;
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wire [22:0] fract_dn_del;
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wire [22:0] fract_dn_del;
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wire [4:0] div_opa_ldz_del;
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wire [4:0] div_opa_ldz_del;
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wire [23:0] fracta_div_del;
|
wire [23:0] fracta_div_del;
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| Line 518... |
Line 558... |
wire [7:0] fi_ldz_2_del;
|
wire [7:0] fi_ldz_2_del;
|
wire inf_out_del, max_out_del;
|
wire inf_out_del, max_out_del;
|
wire [5:0] fi_ldz_del;
|
wire [5:0] fi_ldz_del;
|
wire rx_del;
|
wire rx_del;
|
wire ez_del;
|
wire ez_del;
|
|
wire lr;
|
|
wire [7:0] shr, shl, exp_div_del;
|
|
|
delay2 #26 ud000(clk, test.u0.fracta, fracta_del);
|
delay2 #26 ud000(clk, test.u0.fracta, fracta_del);
|
delay2 #26 ud001(clk, test.u0.fractb, fractb_del);
|
delay2 #26 ud001(clk, test.u0.fractb, fractb_del);
|
delay1 #2 ud002(clk, {g,r,s}, grs_del);
|
delay1 #2 ud002(clk, {g,r,s}, grs_del);
|
delay1 #0 ud004(clk, dn, dn_del);
|
delay1 #0 ud004(clk, dn, dn_del);
|
| Line 541... |
Line 583... |
delay1 #0 ud025(clk, inf_out, inf_out_del);
|
delay1 #0 ud025(clk, inf_out, inf_out_del);
|
delay1 #0 ud026(clk, max_num, max_num_del);
|
delay1 #0 ud026(clk, max_num, max_num_del);
|
delay1 #5 ud027(clk, fi_ldz, fi_ldz_del);
|
delay1 #5 ud027(clk, fi_ldz, fi_ldz_del);
|
delay1 #0 ud028(clk, rem_00, rx_del);
|
delay1 #0 ud028(clk, rem_00, rx_del);
|
|
|
|
delay1 #0 ud029(clk, left_right, lr);
|
|
delay1 #7 ud030(clk, shift_right, shr);
|
|
delay1 #7 ud031(clk, shift_left, shl);
|
|
delay1 #22 ud032(clk, fract_out_rnd2a, fract_out_rnd2a_del);
|
|
|
|
delay1 #7 ud033(clk, exp_div, exp_div_del);
|
|
|
always @(test.error_event)
|
always @(test.error_event)
|
begin
|
begin
|
|
|
$display("\n----------------------------------------------");
|
$display("\n----------------------------------------------");
|
|
|
$display("ERROR: GRS: %b exp_ovf: %b dn: %h exp_in: %h exp_out: %h, exp_rnd_adj2a: %b",
|
$display("ERROR: GRS: %b exp_ovf: %b dn: %h exp_in: %h exp_out: %h, exp_rnd_adj2a: %b",
|
grs_del, exp_ovf_del, dn_del, exp_in_del, exp_out_del, exp_rnd_adj2a_del);
|
grs_del, exp_ovf_del, dn_del, exp_in_del, exp_out_del, exp_rnd_adj2a_del);
|
|
|
$display(" div_opa: %b, div_opb: %b, rem_00: %b",
|
$display(" div_opa: %b, div_opb: %b, rem_00: %b, exp_div: %h",
|
fracta_div_del, fractb_div_del, rx_del);
|
fracta_div_del, fractb_div_del, rx_del, exp_div_del);
|
|
|
|
$display(" lr: %b, shl: %h, shr: %h",
|
|
lr, shl, shr);
|
|
|
|
|
$display(" overflow: %b, fract_in=%b fa:%h fb:%h",
|
$display(" overflow: %b, fract_in=%b fa:%h fb:%h",
|
overflow_del, fract_in_del, fracta_del, fractb_del);
|
overflow_del, fract_in_del, fracta_del, fractb_del);
|
|
|
$display(" div_opa_ldz: %h, div_inf: %b, inf_out: %b, max_num: %b, fi_ldz: %h, fi_ldz_2: %h",
|
$display(" div_opa_ldz: %h, div_inf: %b, inf_out: %b, max_num: %b, fi_ldz: %h, fi_ldz_2: %h",
|
div_opa_ldz_del, div_inf_del, inf_out_del, max_num_del, fi_ldz_del, fi_ldz_2_del);
|
div_opa_ldz_del, div_inf_del, inf_out_del, max_num_del, fi_ldz_del, fi_ldz_2_del);
|
|
|
$display(" fract_out_x: %b, fract_trunc: %b\n",
|
$display(" fract_out_x: %b, fract_out_rnd2a_del: %h, fract_trunc: %b\n",
|
fract_out_x_del, trunc_xx_del);
|
fract_out_x_del, fract_out_rnd2a_del, trunc_xx_del);
|
end
|
end
|
|
|
|
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
