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Line 91... |
signal s_op_0 : std_logic;
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signal s_op_0 : std_logic;
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signal s_expo3 : std_logic_vector(8 downto 0);
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signal s_expo3 : std_logic_vector(8 downto 0);
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signal s_infa, s_infb : std_logic;
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signal s_infa, s_infb : std_logic;
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signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic;
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signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic;
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signal s_opa_dn, s_opb_dn : std_logic;
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begin
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begin
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-- Input Register
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-- Input Register
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process(clk_i)
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process(clk_i)
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| Line 144... |
Line 143... |
process(clk_i)
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process(clk_i)
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variable v_shr1, v_shl1 : std_logic_vector(9 downto 0);
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variable v_shr1, v_shl1 : std_logic_vector(9 downto 0);
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if s_exp_10a(9)='1' or s_exp_10a="0000000000" then
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if s_exp_10a(9)='1' or s_exp_10a="0000000000" then
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v_shr1 := "0000000001" - s_exp_10a;
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v_shr1 := "0000000001" - s_exp_10a + ("000000000"&s_carry);
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v_shl1 := (others =>'0');
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v_shl1 := (others =>'0');
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s_expo1 <= "000000001";
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s_expo1 <= "000000001";
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else
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else
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if s_exp_10b(9)='1' or s_exp_10b="0000000000" then
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if s_exp_10b(9)='1' or s_exp_10b="0000000000" then
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v_shr1 := (others =>'0');
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v_shr1 := (others =>'0');
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s_overflow <= '1' when s_expo3 = "011111111" and (s_infa or s_infb)='0' else '0';
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s_overflow <= '1' when s_expo3 = "011111111" and (s_infa or s_infb)='0' else '0';
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s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_frac2a(22 downto 0)) or s_overflow)='1' else '0';
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s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_frac2a(22 downto 0)) or s_overflow)='1' else '0';
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process(s_sign_i, s_expo3, s_frac3, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow)
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process(s_sign_i, s_expo3, s_frac3, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_r_zeros)
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begin
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begin
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if (s_nan_in or s_nan_op)='1' then
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if (s_nan_in or s_nan_op)='1' then
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s_output_o <= s_sign_i & QNAN;
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s_output_o <= s_sign_i & QNAN;
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elsif (s_infa or s_infb)='1' or s_overflow='1' then
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elsif (s_infa or s_infb)='1' or s_overflow='1' then
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s_output_o <= s_sign_i & INF;
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s_output_o <= s_sign_i & INF;
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elsif s_r_zeros=48 then
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s_output_o <= s_sign_i & ZERO_VECTOR;
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else
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else
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s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_frac3(22 downto 0);
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s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_frac3(22 downto 0);
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end if;
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end if;
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end process;
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end process;
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