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-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: component package
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library work;
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use work.fpupack.all;
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package comppack is
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--- Component Declartions ---
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--***Add/Substract units***
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component pre_norm_addsub is
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port(clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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opb_i : in std_logic_vector(31 downto 0);
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fracta_28_o : out std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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fractb_28_o : out std_logic_vector(27 downto 0);
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exp_o : out std_logic_vector(7 downto 0));
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end component;
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component addsub_28 is
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port(clk_i : in std_logic;
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fpu_op_i : in std_logic;
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fracta_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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fractb_i : in std_logic_vector(27 downto 0);
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signa_i : in std_logic;
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signb_i : in std_logic;
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fract_o : out std_logic_vector(27 downto 0);
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sign_o : out std_logic);
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end component;
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component post_norm_addsub is
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port(clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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opb_i : in std_logic_vector(31 downto 0);
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fract_28_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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exp_i : in std_logic_vector(7 downto 0);
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sign_i : in std_logic;
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fpu_op_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(31 downto 0);
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ine_o : out std_logic
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);
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end component;
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--***Multiplication units***
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component pre_norm_mul is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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opb_i : in std_logic_vector(31 downto 0);
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exp_10_o : out std_logic_vector(9 downto 0);
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fracta_24_o : out std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
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fractb_24_o : out std_logic_vector(23 downto 0)
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);
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end component;
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component mul_24 is
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port(
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clk_i : in std_logic;
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fracta_i : in std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
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fractb_i : in std_logic_vector(23 downto 0);
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signa_i : in std_logic;
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signb_i : in std_logic;
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start_i : in std_logic;
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fract_o : out std_logic_vector(47 downto 0);
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sign_o : out std_logic;
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ready_o : out std_logic
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);
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end component;
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component serial_mul is
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port(
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clk_i : in std_logic;
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fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
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fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
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signa_i : in std_logic;
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signb_i : in std_logic;
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start_i : in std_logic;
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fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
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sign_o : out std_logic;
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ready_o : out std_logic
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);
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end component;
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component post_norm_mul is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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opb_i : in std_logic_vector(31 downto 0);
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exp_10_i : in std_logic_vector(9 downto 0);
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fract_48_i : in std_logic_vector(47 downto 0); -- hidden(1) & fraction(23)
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sign_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(31 downto 0);
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ine_o : out std_logic
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);
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end component;
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--***Division units***
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component pre_norm_div is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
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dvdnd_50_o : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
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dvsor_27_o : out std_logic_vector(FRAC_WIDTH+3 downto 0)
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);
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end component;
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component serial_div is
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port(
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clk_i : in std_logic;
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dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)
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dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
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sign_dvd_i : in std_logic;
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sign_div_i : in std_logic;
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start_i : in std_logic;
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ready_o : out std_logic;
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qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
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rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
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sign_o : out std_logic;
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div_zero_o : out std_logic
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);
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end component;
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component post_norm_div is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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qutnt_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
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rmndr_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
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exp_10_i : in std_logic_vector(EXP_WIDTH+1 downto 0);
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sign_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
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ine_o : out std_logic
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);
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end component;
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--***Square units***
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component pre_norm_sqrt is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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fracta_52_o : out std_logic_vector(51 downto 0);
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exp_o : out std_logic_vector(7 downto 0));
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end component;
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component sqrt is
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generic (RD_WIDTH: integer; SQ_WIDTH: integer); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)
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port(
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clk_i : in std_logic;
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rad_i : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)
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start_i : in std_logic;
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ready_o : out std_logic;
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sqr_o : out std_logic_vector(SQ_WIDTH-1 downto 0);
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ine_o : out std_logic);
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end component;
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component post_norm_sqrt is
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port( clk_i : in std_logic;
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opa_i : in std_logic_vector(31 downto 0);
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fract_26_i : in std_logic_vector(25 downto 0); -- hidden(1) & fraction(11)
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exp_i : in std_logic_vector(7 downto 0);
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ine_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(31 downto 0);
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ine_o : out std_logic);
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end component;
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end comppack;
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