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-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: multiplication entity for the multiplication unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library work;
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use work.fpupack.all;
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entity mul_24 is
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port(
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clk_i : in std_logic;
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fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
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fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
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signa_i : in std_logic;
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signb_i : in std_logic;
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start_i : in std_logic;
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fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
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sign_o : out std_logic;
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ready_o : out std_logic
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);
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end mul_24;
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architecture rtl of mul_24 is
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signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH downto 0);
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signal s_signa_i, s_signb_i, s_sign_o : std_logic;
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signal s_fract_o: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
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signal s_start_i, s_ready_o : std_logic;
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signal a_h, a_l, b_h, b_l : std_logic_vector(11 downto 0);
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signal a_h_h, a_h_l, b_h_h, b_h_l, a_l_h, a_l_l, b_l_h, b_l_l : std_logic_vector(5 downto 0);
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type op_6 is array (7 downto 0) of std_logic_vector(5 downto 0);
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type prod_6 is array (3 downto 0) of op_6;
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type prod_48 is array (4 downto 0) of std_logic_vector(47 downto 0);
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type sum_24 is array (3 downto 0) of std_logic_vector(23 downto 0);
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type a is array (3 downto 0) of std_logic_vector(23 downto 0);
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type prod_24 is array (3 downto 0) of a;
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signal prod : prod_6;
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signal sum : sum_24;
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signal prod_a_b : prod_48;
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signal count : integer range 0 to 4;
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type t_state is (waiting,busy);
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signal s_state : t_state;
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signal prod2 : prod_24;
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begin
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-- Input Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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s_fracta_i <= fracta_i;
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s_fractb_i <= fractb_i;
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s_signa_i<= signa_i;
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s_signb_i<= signb_i;
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s_start_i<=start_i;
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end if;
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end process;
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-- Output Register
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--process(clk_i)
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--begin
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-- if rising_edge(clk_i) then
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fract_o <= s_fract_o;
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sign_o <= s_sign_o;
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ready_o<=s_ready_o;
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-- end if;
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--end process;
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-- FSM
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_start_i ='1' then
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s_state <= busy;
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count <= 0;
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elsif count=4 and s_state=busy then
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s_state <= waiting;
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s_ready_o <= '1';
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count <=0;
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elsif s_state=busy then
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count <= count + 1;
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else
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s_state <= waiting;
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s_ready_o <= '0';
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end if;
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end if;
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end process;
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s_sign_o <= s_signa_i xor s_signb_i;
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--"000000000000"
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-- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l
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-- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l
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a_h <= s_fracta_i(23 downto 12);
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a_l <= s_fracta_i(11 downto 0);
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b_h <= s_fractb_i(23 downto 12);
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b_l <= s_fractb_i(11 downto 0);
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a_h_h <= a_h(11 downto 6);
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a_h_l <= a_h(5 downto 0);
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b_h_h <= b_h(11 downto 6);
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b_h_l <= b_h(5 downto 0);
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a_l_h <= a_l(11 downto 6);
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a_l_l <= a_l(5 downto 0);
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b_l_h <= b_l(11 downto 6);
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b_l_l <= b_l(5 downto 0);
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prod(0)(0) <= a_h_h; prod(0)(1) <= b_h_h;
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prod(0)(2) <= a_h_h; prod(0)(3) <= b_h_l;
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prod(0)(4) <= a_h_l; prod(0)(5) <= b_h_h;
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prod(0)(6) <= a_h_l; prod(0)(7) <= b_h_l;
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prod(1)(0) <= a_h_h; prod(1)(1) <= b_l_h;
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prod(1)(2) <= a_h_h; prod(1)(3) <= b_l_l;
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prod(1)(4) <= a_h_l; prod(1)(5) <= b_l_h;
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prod(1)(6) <= a_h_l; prod(1)(7) <= b_l_l;
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prod(2)(0) <= a_l_h; prod(2)(1) <= b_h_h;
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prod(2)(2) <= a_l_h; prod(2)(3) <= b_h_l;
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prod(2)(4) <= a_l_l; prod(2)(5) <= b_h_h;
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prod(2)(6) <= a_l_l; prod(2)(7) <= b_h_l;
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prod(3)(0) <= a_l_h; prod(3)(1) <= b_l_h;
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prod(3)(2) <= a_l_h; prod(3)(3) <= b_l_l;
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prod(3)(4) <= a_l_l; prod(3)(5) <= b_l_h;
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prod(3)(6) <= a_l_l; prod(3)(7) <= b_l_l;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if count < 4 then
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prod2(count)(0) <= (prod(count)(0)*prod(count)(1))&"000000000000";
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prod2(count)(1) <= "000000"&(prod(count)(2)*prod(count)(3))&"000000";
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prod2(count)(2) <= "000000"&(prod(count)(4)*prod(count)(5))&"000000";
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prod2(count)(3) <= "000000000000"&(prod(count)(6)*prod(count)(7));
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end if;
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end if;
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end process;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if count > 0 and s_state=busy then
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sum(count-1) <= prod2(count-1)(0) + prod2(count-1)(1) + prod2(count-1)(2) + prod2(count-1)(3);
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end if;
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end if;
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end process;
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-- Last stage
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prod_a_b(0) <= sum(0)&"000000000000000000000000";
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prod_a_b(1) <= "000000000000"&sum(1)&"000000000000";
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prod_a_b(2) <= "000000000000"&sum(2)&"000000000000";
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prod_a_b(3) <= "000000000000000000000000"&sum(3);
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prod_a_b(4) <= prod_a_b(0) + prod_a_b(1) + prod_a_b(2) + prod_a_b(3);
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s_fract_o <= prod_a_b(4);
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end rtl;
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