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-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: post-normalization entity for the division unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.fpupack.all;
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entity post_norm_div is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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qutnt_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
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rmndr_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
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exp_10_i : in std_logic_vector(EXP_WIDTH+1 downto 0);
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sign_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
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ine_o : out std_logic
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);
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end post_norm_div;
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architecture rtl of post_norm_div is
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-- input&output register signals
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signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_qutnt_i, s_rmndr_i : std_logic_vector(FRAC_WIDTH+3 downto 0);
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signal s_r_zeros : std_logic_vector(5 downto 0);
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signal s_exp_10_i : std_logic_vector(EXP_WIDTH+1 downto 0);
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signal s_sign_i : std_logic;
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signal s_rmode_i : std_logic_vector(1 downto 0);
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signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_ine_o, s_overflow : std_logic;
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signal s_opa_dn, s_opb_dn : std_logic;
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signal s_qutdn : std_logic;
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signal s_exp_10b : std_logic_vector(9 downto 0);
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signal s_shr1, s_shl1 : std_logic_vector(5 downto 0);
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signal s_shr2 : std_logic;
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signal s_expo1, s_expo2, s_expo3 : std_logic_vector(8 downto 0);
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signal s_fraco1 : std_logic_vector(26 downto 0);
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signal s_frac_rnd, s_fraco2 : std_logic_vector(24 downto 0);
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signal s_guard, s_round, s_sticky, s_roundup : std_logic;
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signal s_lost : std_logic;
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signal s_op_0, s_opab_0, s_opb_0 : std_logic;
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signal s_infa, s_infb : std_logic;
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signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic;
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signal s_inf_result: std_logic;
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begin
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-- Input Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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s_opa_i <= opa_i;
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s_opb_i <= opb_i;
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s_expa <= opa_i(30 downto 23);
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s_expb <= opb_i(30 downto 23);
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s_qutnt_i <= qutnt_i;
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s_rmndr_i <= rmndr_i;
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s_exp_10_i <= exp_10_i;
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s_sign_i <= sign_i;
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s_rmode_i <= rmode_i;
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end if;
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end process;
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-- Output Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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output_o <= s_output_o;
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ine_o <= s_ine_o;
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end if;
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end process;
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-- qutnt_i
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-- 26 25 3
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-- | | |
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-- h fffffffffffffffffffffff grs
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--*** Stage 1 ****
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-- figure out the exponent and howmuch the fraction has to be shiftd right/left
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s_opa_dn <= '1' when or_reduce(s_expa)='0' and or_reduce(opa_i(22 downto 0))='1' else '0';
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s_opb_dn <= '1' when or_reduce(s_expb)='0' and or_reduce(opb_i(22 downto 0))='1' else '0';
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s_qutdn <= not s_qutnt_i(26);
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s_exp_10b <= s_exp_10_i - ("000000000"&s_qutdn);
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process(clk_i)
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variable v_shr, v_shl : std_logic_vector(9 downto 0);
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begin
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if rising_edge(clk_i) then
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if s_exp_10b(9)='1' or s_exp_10b="0000000000" then
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v_shr := ("0000000001" - s_exp_10b) - s_qutdn;
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v_shl := (others =>'0');
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s_expo1 <= "000000001";
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elsif s_exp_10b(8)='1' then
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v_shr := (others =>'0');
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v_shl := (others =>'0');
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s_expo1 <= s_exp_10b(8 downto 0);
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else
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v_shr := (others =>'0');
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v_shl := "000000000"& s_qutdn;
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s_expo1 <= s_exp_10b(8 downto 0);
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end if;
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if v_shr(6)='1' then
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s_shr1 <= "111111";
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else
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s_shr1 <= v_shr(5 downto 0);
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end if;
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s_shl1 <= v_shl(5 downto 0);
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end if;
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end process;
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-- *** Stage 2 ***
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-- Shifting the fraction and rounding
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-- shift the fraction
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_shr1 /= "000000" then
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s_fraco1 <= shr(s_qutnt_i, s_shr1);
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else
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s_fraco1 <= shl(s_qutnt_i, s_shl1);
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end if;
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end if;
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end process;
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s_expo2 <= s_expo1 - "000000001" when s_fraco1(26)='0' else s_expo1;
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s_r_zeros <= count_r_zeros(s_qutnt_i);
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s_lost <= '1' when (s_shr1+("00000"&s_shr2)) > s_r_zeros else '0';
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-- ***Stage 3***
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-- Rounding
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s_guard <= s_fraco1(2);
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s_round <= s_fraco1(1);
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s_sticky <= s_fraco1(0) or or_reduce(s_rmndr_i);
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s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
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( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
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( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
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'0'; -- round to zero(truncate = no rounding)
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s_frac_rnd <= ("0"&s_fraco1(26 downto 3)) + '1' when s_roundup='1' else "0"&s_fraco1(26 downto 3);
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s_shr2 <= s_frac_rnd(24);
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_shr2='1' then
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s_expo3 <= s_expo2 + "1";
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s_fraco2 <= "0"&s_frac_rnd(24 downto 1);
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else
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s_expo3 <= s_expo2;
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s_fraco2 <= s_frac_rnd;
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end if;
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end if;
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end process;
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---
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---***Stage 4****
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-- Output
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s_op_0 <= not ( or_reduce(s_opa_i(30 downto 0)) and or_reduce(s_opb_i(30 downto 0)) );
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s_opab_0 <= not ( or_reduce(s_opa_i(30 downto 0)) or or_reduce(s_opb_i(30 downto 0)) );
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s_opb_0 <= not or_reduce(s_opb_i(30 downto 0));
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s_infa <= '1' when s_expa="11111111" else '0';
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s_infb <= '1' when s_expb="11111111" else '0';
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s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
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s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
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s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0';
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s_nan_op <= '1' when (s_infa and s_infb)='1' or s_opab_0='1' else '0';-- 0 / 0, inf / inf
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s_inf_result <= '1' when (and_reduce(s_expo3(7 downto 0)) or s_expo3(8))='1' or s_opb_0='1' else '0';
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s_overflow <= '1' when s_inf_result='1' and (s_infa or s_infb)='0' and s_opb_0='0' else '0';
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s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_fraco1(2 downto 0)) or s_overflow or or_reduce(s_rmndr_i))='1' else '0';
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process(s_sign_i, s_expo3, s_fraco2, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_inf_result, s_op_0)
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begin
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if (s_nan_in or s_nan_op)='1' then
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s_output_o <= '1' & QNAN;
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elsif (s_infa or s_infb)='1' or s_overflow='1' or s_inf_result='1' then
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s_output_o <= s_sign_i & INF;
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elsif s_op_0='1' then
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s_output_o <= s_sign_i & ZERO_VECTOR;
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else
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s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_fraco2(22 downto 0);
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end if;
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end process;
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end rtl;
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