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-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: pre-normalization entity for the square-root unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.fpupack.all;
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entity pre_norm_sqrt is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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fracta_52_o : out std_logic_vector(2*(FRAC_WIDTH+3)-1 downto 0);
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exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0)
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);
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end pre_norm_sqrt;
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architecture rtl of pre_norm_sqrt is
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signal s_expa : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_exp_o, s_exp_tem : std_logic_vector(EXP_WIDTH downto 0);
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signal s_fracta : std_logic_vector(FRAC_WIDTH-1 downto 0);
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signal s_fracta_24 : std_logic_vector(FRAC_WIDTH downto 0);
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signal s_fracta_52_o, s_fracta1_52_o, s_fracta2_52_o : std_logic_vector(2*(FRAC_WIDTH+3)-1 downto 0);
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signal s_sqr_zeros_o : std_logic_vector(5 downto 0);
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signal s_opa_dn : std_logic;
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begin
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s_expa <= opa_i(30 downto 23);
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s_fracta <= opa_i(22 downto 0);
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exp_o <= s_exp_o(7 downto 0);
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fracta_52_o <= s_fracta_52_o;
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-- opa or opb is denormalized
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s_opa_dn <= not or_reduce(s_expa);
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s_fracta_24 <= (not s_opa_dn) & s_fracta;
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-- count leading zeros
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s_sqr_zeros_o <= count_l_zeros(s_fracta_24 );
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-- adjust the exponent
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s_exp_tem <= ("0"&s_expa)+"001111111" - ("000"&s_sqr_zeros_o);
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if or_reduce(opa_i(30 downto 0))='1' then
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s_exp_o <= ("0"&s_exp_tem(8 downto 1));
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else
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s_exp_o <= "000000000";
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end if;
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end if;
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end process;
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-- left-shift the radicand
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s_fracta1_52_o <= shl(s_fracta_24, s_sqr_zeros_o) & "0000000000000000000000000000";
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s_fracta2_52_o <= '0' & shl(s_fracta_24, s_sqr_zeros_o) & "000000000000000000000000000";
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s_fracta_52_o <= s_fracta1_52_o when s_expa(0)='0' else s_fracta2_52_o;
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end rtl;
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