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---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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ENTITY fpu_add IS
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PORT(
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clk : IN std_logic;
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rst : IN std_logic;
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enable : IN std_logic;
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opa : IN std_logic_vector (63 DOWNTO 0);
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opb : IN std_logic_vector (63 DOWNTO 0);
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sign : OUT std_logic;
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sum_3 : OUT std_logic_vector (55 DOWNTO 0);
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exponent_2 : OUT std_logic_vector (10 DOWNTO 0)
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);
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-- Declarations
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END fpu_add;
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architecture rtl of fpu_add is
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signal exponent_a : std_logic_vector(10 downto 0);
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signal exponent_b : std_logic_vector(10 downto 0);
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signal mantissa_a : std_logic_vector(51 downto 0);
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signal mantissa_b : std_logic_vector(51 downto 0);
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signal exponent_small : std_logic_vector(10 downto 0);
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signal exponent_large : std_logic_vector(10 downto 0);
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signal mantissa_small : std_logic_vector(51 downto 0);
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signal mantissa_large : std_logic_vector(51 downto 0);
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signal small_is_denorm : std_logic;
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signal large_is_denorm : std_logic;
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signal large_norm_small_denorm : std_logic_vector(10 downto 0);
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signal exponent_diff : std_logic_vector(10 downto 0);
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signal large_add : std_logic_vector(55 downto 0);
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signal small_add : std_logic_vector(55 downto 0);
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signal small_shift : std_logic_vector(55 downto 0);
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signal small_shift_nonzero : std_logic;
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signal small_is_nonzero : std_logic;
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signal small_fraction_enable : std_logic;
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signal small_shift_2 : std_logic_vector(55 downto 0);
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signal small_shift_3 : std_logic_vector(55 downto 0);
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signal sum : std_logic_vector(55 downto 0);
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signal sum_2 : std_logic_vector(55 downto 0);
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signal sum_overflow : std_logic;
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signal exponent : std_logic_vector(10 downto 0);
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signal sum_leading_one : std_logic;
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signal denorm_to_norm : std_logic;
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signal exp_diff_int : integer;
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begin
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small_shift_nonzero <= or_reduce(small_shift);
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small_is_nonzero <= or_reduce(exponent_small) or or_reduce(mantissa_small(51 downto 0));
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small_fraction_enable <= small_is_nonzero and not small_shift_nonzero;
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small_shift_2 <= "00000000000000000000000000000000000000000000000000000001";
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sum_overflow <= sum(55); -- sum[55] will be 0 if there was no carry from adding the 2 numbers
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sum_leading_one <= sum_2(54); -- this is where the leading one resides, unless denorm
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--exp_diff_int <= to_integer(exponent_diff);
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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sign <= '0';
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exponent_a <= (others =>'0');
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exponent_b <= (others =>'0');
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mantissa_a <= (others =>'0');
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mantissa_b <= (others =>'0');
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exponent_small <= (others =>'0');
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exponent_large <= (others =>'0');
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mantissa_small <= (others =>'0');
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mantissa_large <= (others =>'0');
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small_is_denorm <= '0';
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large_is_denorm <= '0';
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large_norm_small_denorm <= (others =>'0');
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exponent_diff <= (others =>'0');
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large_add <= (others =>'0');
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small_add <= (others =>'0');
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small_shift <= (others =>'0');
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small_shift_3 <= (others =>'0');
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sum <= (others =>'0');
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sum_2 <= (others =>'0');
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sum_3 <= (others =>'0');
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exponent <= (others =>'0');
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denorm_to_norm <= '0';
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exponent_2 <= (others =>'0');
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elsif (enable = '1') then
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sign <= opa(63);
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exponent_a <= opa(62 downto 52);
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exponent_b <= opb(62 downto 52);
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mantissa_a <= opa(51 downto 0);
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mantissa_b <= opb(51 downto 0);
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if (exponent_a > exponent_b) then
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exponent_small <= exponent_b;
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exponent_large <= exponent_a;
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mantissa_small <= mantissa_b;
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mantissa_large <= mantissa_a;
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else
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exponent_small <= exponent_a;
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exponent_large <= exponent_b;
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mantissa_small <= mantissa_a;
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mantissa_large <= mantissa_b;
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end if;
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if (exponent_small > 0) then
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small_is_denorm <= '0';
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else
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small_is_denorm <= '1';
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end if;
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if (exponent_large > 0) then
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large_is_denorm <= '0';
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else
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large_is_denorm <= '1';
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end if;
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if (small_is_denorm = '1' and large_is_denorm = '0') then
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large_norm_small_denorm <= "00000000001";
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else
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large_norm_small_denorm <= "00000000000";
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end if;
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exponent_diff <= exponent_large - exponent_small - large_norm_small_denorm;
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large_add <= '0' & not large_is_denorm & mantissa_large & "00";
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small_add <= '0' & not small_is_denorm & mantissa_small & "00";
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small_shift <= shr(small_add, exponent_diff);
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if (small_fraction_enable = '1') then
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small_shift_3 <= small_shift_2;
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else
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small_shift_3 <= small_shift;
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end if;
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sum <= large_add + small_shift_3;
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if (sum_overflow = '1') then
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sum_2 <= shr(sum, conv_std_logic_vector('1', 56));
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else
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sum_2 <= sum;
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end if;
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sum_3 <= sum_2;
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if (sum_overflow = '1') then
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exponent <= exponent_large + 1;
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else
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exponent <= exponent_large;
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end if;
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denorm_to_norm <= sum_leading_one and large_is_denorm;
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if (denorm_to_norm = '1') then
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exponent_2 <= exponent + 1;
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else
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exponent_2 <= exponent;
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end if;
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end if;
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end process;
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end rtl;
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