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https://opencores.org/ocsvn/fpu_double/fpu_double/trunk
[/] [fpu_double/] [trunk/] [fpu_div.vhd] - Diff between revs 5 and 14
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| Rev 5 |
Rev 14 |
| Line 151... |
Line 151... |
mantissa_3 <= quotient_out(51 downto 0);
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mantissa_3 <= quotient_out(51 downto 0);
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mantissa_4 <= mantissa_2 when quotient_msb = '1' else mantissa_3;
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mantissa_4 <= mantissa_2 when quotient_msb = '1' else mantissa_3;
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mantissa_5 <= mantissa_2 when expon_final_4 = "000000000001" else mantissa_4;
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mantissa_5 <= mantissa_2 when expon_final_4 = "000000000001" else mantissa_4;
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mantissa_6 <= mantissa_1 when expon_final_4_et0 = '1' else mantissa_5;
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mantissa_6 <= mantissa_1 when expon_final_4_et0 = '1' else mantissa_5;
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remainder_a <= quotient_out(53 downto 0) & remainder_msb & remainder_out(52 downto 0);
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remainder_a <= quotient_out(53 downto 0) & remainder_msb & remainder_out(52 downto 0);
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remainder_1 <= remainder_b(107 downto 52);
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remainder_1 <= remainder_b(107 downto 53) & or_reduce(remainder_b(52 downto 0));
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remainder_2 <= quotient_out(0) & remainder_msb & remainder_out(52 downto 0) & '0' ;
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remainder_2 <= quotient_out(0) & remainder_msb & remainder_out(52 downto 0) & '0' ;
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remainder_3 <= remainder_msb & remainder_out(52 downto 0) & "00" ;
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remainder_3 <= remainder_msb & remainder_out(52 downto 0) & "00" ;
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remainder_4 <= remainder_2 when quotient_msb = '1' else remainder_3;
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remainder_4 <= remainder_2 when quotient_msb = '1' else remainder_3;
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remainder_5 <= remainder_2 when expon_final_4 = "000000000001" else remainder_4;
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remainder_5 <= remainder_2 when expon_final_4 = "000000000001" else remainder_4;
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remainder_6 <= remainder_1 when expon_final_4_et0 = '1' else remainder_5;
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remainder_6 <= remainder_1 when expon_final_4_et0 = '1' else remainder_5;
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