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---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.comppack.all;
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use work.fpupack.all;
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ENTITY fpu_double IS
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PORT(
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clk, rst, enable : IN std_logic;
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rmode : IN std_logic_vector (1 DOWNTO 0);
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fpu_op : IN std_logic_vector (2 DOWNTO 0);
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opa, opb : IN std_logic_vector (63 DOWNTO 0);
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out_fp: OUT std_logic_vector (63 DOWNTO 0);
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ready, underflow, overflow, inexact : OUT std_logic;
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exception, invalid : OUT std_logic
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);
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END fpu_double;
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-- FPU Operations (fpu_op):
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--========================
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-- 0 = add
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-- 1 = sub
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-- 2 = mul
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-- 3 = div
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--Rounding Modes (rmode):
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--=======================
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-- 0 = round_nearest_even
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-- 1 = round_to_zero
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-- 2 = round_up
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-- 3 = round_down
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architecture rtl of fpu_double is
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signal opa_reg : std_logic_vector(63 downto 0);
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signal opb_reg : std_logic_vector(63 downto 0);
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signal fpu_op_reg : std_logic_vector(2 downto 0);
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signal rmode_reg : std_logic_vector(1 downto 0);
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signal enable_reg : std_logic;
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signal enable_reg_1 : std_logic; -- high for one clock cycle
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signal enable_reg_2 : std_logic; -- high for one clock cycle
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signal enable_reg_3 : std_logic; -- high for two clock cycles
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signal op_enable : std_logic;
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signal count_cycles : std_logic_vector(6 downto 0);
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signal count_ready : std_logic_vector(6 downto 0);
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signal count_busy : std_logic;
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signal ready_0 : std_logic;
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signal ready_1 : std_logic;
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signal underflow_0 : std_logic;
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signal overflow_0 : std_logic;
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signal inexact_0 : std_logic;
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signal exception_0 : std_logic;
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signal invalid_0 : std_logic;
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signal add_enable_0 : std_logic;
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signal add_enable_1 : std_logic;
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signal add_enable : std_logic;
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signal sub_enable_0 : std_logic;
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signal sub_enable_1 : std_logic;
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signal sub_enable : std_logic;
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signal mul_enable : std_logic;
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signal div_enable : std_logic;
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signal except_enable : std_logic;
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signal sum_out : std_logic_vector(55 downto 0);
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signal diff_out : std_logic_vector(55 downto 0);
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signal addsub_out : std_logic_vector(55 downto 0);
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signal mul_out : std_logic_vector(55 downto 0);
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signal div_out : std_logic_vector(55 downto 0);
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signal mantissa_round : std_logic_vector(55 downto 0);
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signal exp_add_out : std_logic_vector(10 downto 0);
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signal exp_sub_out : std_logic_vector(10 downto 0);
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signal exp_mul_out : std_logic_vector(11 downto 0);
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signal exp_div_out : std_logic_vector(11 downto 0);
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signal exponent_round : std_logic_vector(11 downto 0);
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signal exp_addsub : std_logic_vector(11 downto 0);
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signal exponent_post_round : std_logic_vector(11 downto 0);
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signal add_sign : std_logic;
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signal sub_sign : std_logic;
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signal mul_sign : std_logic;
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signal div_sign : std_logic;
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signal addsub_sign : std_logic;
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signal sign_round : std_logic;
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signal out_round : std_logic_vector(63 downto 0);
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signal out_except : std_logic_vector(63 downto 0);
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begin
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i_fpu_add: fpu_add
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port map (
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clk => clk , rst => rst , enable => add_enable , opa => opa_reg , opb => opb_reg ,
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sign => add_sign , sum_3 => sum_out , exponent_2 => exp_add_out);
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i_fpu_sub: fpu_sub
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port map (
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clk => clk , rst => rst , enable => sub_enable , opa => opa_reg , opb => opb_reg ,
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fpu_op => fpu_op_reg , sign => sub_sign , diff_2 => diff_out ,
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exponent_2 => exp_sub_out);
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i_fpu_mul: fpu_mul
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port map (
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clk => clk , rst => rst , enable => mul_enable , opa => opa_reg , opb => opb_reg ,
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sign => mul_sign , product_7 => mul_out , exponent_5 => exp_mul_out);
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i_fpu_div: fpu_div
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port map (
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clk => clk , rst => rst , enable => div_enable , opa => opa_reg , opb => opb_reg ,
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sign => div_sign , mantissa_7 => div_out , exponent_out => exp_div_out);
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i_fpu_round: fpu_round
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port map (
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clk => clk , rst => rst , enable => op_enable , round_mode => rmode_reg ,
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sign_term => sign_round , mantissa_term => mantissa_round , exponent_term => exponent_round ,
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round_out => out_round , exponent_final => exponent_post_round);
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i_fpu_exceptions: fpu_exceptions
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port map (
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clk => clk , rst => rst , enable => op_enable , rmode => rmode_reg ,
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opa => opa_reg , opb => opb_reg ,
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in_except => out_round , exponent_in => exponent_post_round ,
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mantissa_in => mantissa_round(1 downto 0) , fpu_op => fpu_op_reg , out_fp => out_except ,
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ex_enable => except_enable , underflow => underflow_0 , overflow => overflow_0 ,
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inexact => inexact_0 , exception => exception_0 , invalid => invalid_0);
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count_busy <= '1' when (count_ready <= count_cycles) else '0';
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add_enable_0 <= '1' when fpu_op_reg = "000" and (opa_reg(63) xor opb_reg(63)) = '0' else '0';
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add_enable_1 <= '1' when (fpu_op_reg = "001") and (opa_reg(63) xor opb_reg(63)) = '1' else '0';
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sub_enable_0 <= '1' when (fpu_op_reg = "000") and (opa_reg(63) xor opb_reg(63)) = '1' else '0';
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sub_enable_1 <= '1' when (fpu_op_reg = "001") and (opa_reg(63) xor opb_reg(63)) = '0' else '0';
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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mantissa_round <= (others =>'0');
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exponent_round <= (others =>'0');
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sign_round <= '0';
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count_cycles <= (others =>'0');
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else
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if (fpu_op_reg = "000") then -- add
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mantissa_round <= addsub_out;
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exponent_round <= exp_addsub;
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sign_round <= addsub_sign;
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count_cycles <= "0010100"; -- 20
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elsif (fpu_op_reg = "001") then -- subtract
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mantissa_round <= addsub_out;
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exponent_round <= exp_addsub;
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sign_round <= addsub_sign;
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count_cycles <= "0010101"; -- 21
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elsif (fpu_op_reg = "010") then
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mantissa_round <= mul_out;
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exponent_round <= exp_mul_out;
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sign_round <= mul_sign;
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count_cycles <= "0011000"; -- 24
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elsif (fpu_op_reg = "011") then
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mantissa_round <= div_out;
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exponent_round <= exp_div_out;
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sign_round <= div_sign;
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count_cycles <= "1000111"; -- 71
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else
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mantissa_round <= (others =>'0');
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exponent_round <= (others =>'0');
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sign_round <= '0';
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count_cycles <= (others =>'0');
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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add_enable <= '0';
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sub_enable <= '0';
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mul_enable <= '0';
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div_enable <= '0';
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addsub_out <= (others =>'0');
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addsub_sign <= '0';
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exp_addsub <= (others =>'0');
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else
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if ((add_enable_0 = '1' or add_enable_1 = '1') and op_enable= '1') then
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add_enable <= '1';
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else
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add_enable <= '0';
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end if;
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if ((sub_enable_0 = '1' or sub_enable_1 = '1') and op_enable = '1') then
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sub_enable <= '1';
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else
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sub_enable <= '0';
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end if;
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if fpu_op_reg = "010" and op_enable = '1' then
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mul_enable <= '1';
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else
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mul_enable <= '0';
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end if;
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if fpu_op_reg = "011" and op_enable = '1' and enable_reg_3 = '1' then
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div_enable <= '1';
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else
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div_enable <= '0';
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end if; -- div_enable needs to be high for two clock cycles
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if add_enable = '1' then
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addsub_out <= sum_out;
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addsub_sign <= add_sign;
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exp_addsub <= '0' & exp_add_out;
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else
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addsub_out <= diff_out;
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addsub_sign <= sub_sign;
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exp_addsub <= '0' & exp_sub_out;
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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count_ready <= (others =>'0');
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elsif (enable_reg_1 = '1') then
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count_ready <= (others =>'0');
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elsif (count_busy = '1') then
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count_ready <= count_ready + "0000001";
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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enable_reg <= '0';
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enable_reg_1 <= '0';
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enable_reg_2 <= '0';
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enable_reg_3 <= '0';
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else
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enable_reg <= enable;
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if enable = '1' and enable_reg = '0' then
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enable_reg_1 <= '1';
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else
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enable_reg_1 <= '0';
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end if;
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enable_reg_2 <= enable_reg_1;
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if enable_reg_1 = '1' or enable_reg_2 = '1' then
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enable_reg_3 <= '1';
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else
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enable_reg_3 <= '0';
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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opa_reg <= (others =>'0');
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opb_reg <= (others =>'0');
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fpu_op_reg <= (others =>'0');
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rmode_reg <= (others =>'0');
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op_enable <= '0';
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elsif (enable_reg_1 = '1') then
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opa_reg <= opa;
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opb_reg <= opb;
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fpu_op_reg <= fpu_op;
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rmode_reg <= rmode;
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op_enable <= '1';
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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ready_0 <= '0';
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ready_1 <= '0';
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ready <= '0';
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elsif (enable_reg_1 = '1') then
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ready_0 <= '0';
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ready_1 <= '0';
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ready <= '0';
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else
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ready_0 <= not count_busy;
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ready_1 <= ready_0;
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ready <= ready_1;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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underflow <= '0';
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overflow <= '0';
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inexact <= '0';
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exception <= '0';
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invalid <= '0';
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out_fp <= (others =>'0');
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elsif (ready_1 = '1') then
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underflow <= underflow_0;
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overflow <= overflow_0;
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inexact <= inexact_0;
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exception <= exception_0;
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invalid <= invalid_0;
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if except_enable = '1' then
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out_fp <= out_except;
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else
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out_fp <= out_round;
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end if;
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end if;
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end process;
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end rtl;
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