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---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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ENTITY fpu_exceptions IS
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PORT(
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clk, rst, enable : IN std_logic;
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rmode : IN std_logic_vector (1 DOWNTO 0);
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opa, opb, in_except : IN std_logic_vector (63 DOWNTO 0);
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exponent_in : IN std_logic_vector (11 DOWNTO 0);
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mantissa_in : IN std_logic_vector (1 DOWNTO 0);
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fpu_op : IN std_logic_vector (2 DOWNTO 0);
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out_fp : OUT std_logic_vector (63 DOWNTO 0);
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ex_enable, underflow, overflow, inexact : OUT std_logic;
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exception, invalid : OUT std_logic
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);
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END fpu_exceptions;
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architecture rtl of fpu_exceptions is
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signal in_et_zero : std_logic;
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signal opa_et_zero : std_logic;
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signal opb_et_zero : std_logic;
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signal add : std_logic;
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signal subtract : std_logic;
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signal multiply : std_logic;
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signal divide : std_logic;
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signal opa_QNaN : std_logic;
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signal opb_QNaN : std_logic;
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signal opa_SNaN : std_logic;
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signal opb_SNaN : std_logic;
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signal opa_pos_inf : std_logic;
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signal opb_pos_inf : std_logic;
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signal opa_neg_inf : std_logic;
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signal opb_neg_inf : std_logic;
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signal opa_inf : std_logic;
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signal opb_inf : std_logic;
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signal NaN_input : std_logic;
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signal SNaN_input : std_logic;
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signal a_NaN : std_logic;
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signal div_by_0 : std_logic;
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signal div_0_by_0 : std_logic;
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signal div_inf_by_inf : std_logic;
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signal div_by_inf : std_logic;
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signal mul_0_by_inf : std_logic;
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signal mul_inf : std_logic;
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signal div_inf : std_logic;
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signal add_inf : std_logic;
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signal sub_inf : std_logic;
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signal addsub_inf_invalid : std_logic;
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signal addsub_inf : std_logic;
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signal out_inf_trigger : std_logic;
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signal out_pos_inf : std_logic;
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signal out_neg_inf : std_logic;
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signal round_nearest : std_logic;
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signal round_to_zero : std_logic;
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signal round_to_pos_inf : std_logic;
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signal round_to_neg_inf : std_logic;
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signal inf_round_down_trigger : std_logic;
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signal mul_uf : std_logic;
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signal div_uf : std_logic;
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signal underflow_trigger : std_logic;
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signal invalid_trigger : std_logic;
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signal overflow_trigger : std_logic;
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signal inexact_trigger : std_logic;
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signal except_trigger : std_logic;
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signal enable_trigger : std_logic;
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signal NaN_out_trigger : std_logic;
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signal SNaN_trigger : std_logic;
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signal exp_2047 : std_logic_vector(10 downto 0);
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signal exp_2046 : std_logic_vector(10 downto 0);
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signal NaN_output_0 : std_logic_vector(62 downto 0);
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signal NaN_output : std_logic_vector(62 downto 0);
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signal mantissa_max : std_logic_vector(51 downto 0);
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signal inf_round_down : std_logic_vector(62 downto 0);
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signal out_inf : std_logic_vector(62 downto 0);
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signal out_0 : std_logic_vector(63 downto 0);
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signal out_1 : std_logic_vector(63 downto 0);
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signal out_2 : std_logic_vector(63 downto 0);
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begin
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exp_2047 <= "11111111111";
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exp_2046 <= "11111111110";
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mantissa_max <= "1111111111111111111111111111111111111111111111111111";
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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in_et_zero <= '0';
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opa_et_zero <= '0';
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opb_et_zero <= '0';
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add <= '0';
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subtract <= '0';
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multiply <= '0';
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divide <= '0';
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opa_QNaN <= '0';
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opb_QNaN <= '0';
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opa_SNaN <= '0';
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opb_SNaN <= '0';
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opa_pos_inf <= '0';
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opb_pos_inf <= '0';
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opa_neg_inf <= '0';
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opb_neg_inf <= '0';
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opa_inf <= '0';
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opb_inf <= '0';
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NaN_input <= '0';
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SNaN_input <= '0';
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a_NaN <= '0';
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div_by_0 <= '0';
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div_0_by_0 <= '0';
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div_inf_by_inf <= '0';
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div_by_inf <= '0';
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mul_0_by_inf <= '0';
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mul_inf <= '0';
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div_inf <= '0';
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add_inf <= '0';
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sub_inf <= '0';
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addsub_inf_invalid <= '0';
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addsub_inf <= '0';
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out_inf_trigger <= '0';
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out_pos_inf <= '0';
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out_neg_inf <= '0';
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round_nearest <= '0';
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round_to_zero <= '0';
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round_to_pos_inf <= '0';
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round_to_neg_inf <= '0';
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inf_round_down_trigger <= '0';
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mul_uf <= '0';
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div_uf <= '0';
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underflow_trigger <= '0';
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invalid_trigger <= '0';
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overflow_trigger <= '0';
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inexact_trigger <= '0';
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except_trigger <= '0';
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enable_trigger <= '0';
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NaN_out_trigger <= '0';
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SNaN_trigger <= '0';
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NaN_output_0 <= (others =>'0');
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NaN_output <= (others =>'0');
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inf_round_down <= (others =>'0');
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out_inf <= (others =>'0');
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out_0 <= (others =>'0');
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out_1 <= (others =>'0');
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out_2 <= (others =>'0');
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elsif (enable = '1') then
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if or_reduce(in_except(62 downto 0)) = '0' then
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in_et_zero <= '1';
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else
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in_et_zero <= '0';
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end if;
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if or_reduce(opa(62 downto 0)) = '0' then
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opa_et_zero <= '1';
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else
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opa_et_zero <= '0';
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end if;
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if or_reduce(opb(62 downto 0)) = '0' then
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opb_et_zero <= '1';
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else
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opb_et_zero <= '0';
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end if;
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if fpu_op = "000" then
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add <= '1';
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else
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add <= '0';
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end if;
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if fpu_op = "001" then
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subtract <= '1';
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else
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subtract <= '0';
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end if;
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if fpu_op = "010" then
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multiply <= '1';
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else
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multiply <= '0';
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end if;
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if fpu_op = "011" then
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divide <= '1';
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else
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divide <= '0';
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end if;
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if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
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opa(51) = '1' then
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opa_QNaN <= '1';
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else
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opa_QNaN <= '0';
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end if;
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if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
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opb(51) = '1' then
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opb_QNaN <= '1';
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else
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opb_QNaN <= '0';
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end if;
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if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
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opa(51) = '0' then
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opa_SNaN <= '1';
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else
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opa_SNaN <= '0';
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end if;
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if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
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opb(51) = '0' then
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opb_SNaN <= '1';
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else
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opb_SNaN <= '0';
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end if;
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if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
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opa(63) = '0' then
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opa_pos_inf <= '1';
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else
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opa_pos_inf <= '0';
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end if;
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if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
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opb(63) = '0' then
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opb_pos_inf <= '1';
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else
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opb_pos_inf <= '0';
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end if;
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if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
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opa(63) = '1' then
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opa_neg_inf <= '1';
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else
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opa_neg_inf <= '0';
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end if;
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if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
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opb(63) = '1' then
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opb_neg_inf <= '1';
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else
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opb_neg_inf <= '0';
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end if;
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if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' then
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opa_inf <= '1';
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else
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opa_inf <= '0';
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end if;
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if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' then
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opb_inf <= '1';
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else
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opb_inf <= '0';
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end if;
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if opa_QNaN = '1' or opb_QNaN = '1' or opa_SNaN = '1' or opb_SNaN = '1' then
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NaN_input <= '1';
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else
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NaN_input <= '0';
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end if;
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if opa_SNaN = '1' or opb_SNaN = '1' then
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SNaN_input <= '1';
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else
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SNaN_input <= '0';
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end if;
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if opa_SNaN = '1' or opa_QNaN = '1' then
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a_NaN <= '1';
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else
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a_NaN <= '0';
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end if;
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if divide = '1' and opb_et_zero = '1' and opa_et_zero = '0' then
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div_by_0 <= '1';
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else
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div_by_0 <= '0';
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end if;
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if divide = '1' and opb_et_zero = '1' and opa_et_zero = '1' then
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div_0_by_0 <= '1';
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else
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div_0_by_0 <= '0';
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end if;
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if divide = '1' and opa_inf = '1' and opb_inf = '1' then
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div_inf_by_inf <= '1';
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else
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div_inf_by_inf <= '0';
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end if;
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if divide = '1' and opa_inf = '0' and opb_inf = '1' then
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div_by_inf <= '1';
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else
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div_by_inf <= '0';
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end if;
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if multiply = '1' and ((opa_inf = '1' and opb_et_zero = '1') or
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(opa_et_zero = '1' and opb_inf = '1')) then
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mul_0_by_inf <= '1';
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else
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mul_0_by_inf <= '0';
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end if;
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if multiply = '1' and (opa_inf = '1' or opb_inf = '1') and
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mul_0_by_inf = '0' then
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mul_inf <= '1';
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else
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mul_inf <= '0';
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end if;
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if divide = '1' and opa_inf = '1' and opb_inf = '0' then
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div_inf <= '1';
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else
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div_inf <= '0';
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end if;
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if add = '1' and (opa_inf = '1' or opb_inf = '1') then
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add_inf <= '1';
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else
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add_inf <= '0';
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end if;
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if subtract = '1' and (opa_inf = '1' or opb_inf = '1') then
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sub_inf <= '1';
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else
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sub_inf <= '0';
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end if;
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if (add = '1' and opa_pos_inf = '1' and opb_neg_inf = '1') or
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(add = '1' and opa_neg_inf = '1' and opb_pos_inf = '1') or
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(subtract = '1' and opa_pos_inf = '1' and opb_pos_inf = '1') or
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(subtract = '1' and opa_neg_inf = '1' and opb_neg_inf = '1') then
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addsub_inf_invalid <= '1';
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else
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addsub_inf_invalid <= '0';
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end if;
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if (add_inf = '1' or sub_inf = '1') and addsub_inf_invalid = '0' then
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addsub_inf <= '1';
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else
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addsub_inf <= '0';
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end if;
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if addsub_inf = '1' or mul_inf = '1' or div_inf = '1' or div_by_0 = '1'
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or (exponent_in > "011111111110") then -- 2046
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out_inf_trigger <= '1';
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else
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out_inf_trigger <= '0';
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end if;
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if out_inf_trigger = '1' and in_except(63) = '0' then
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out_pos_inf <= '1';
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else
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out_pos_inf <= '0';
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end if;
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if out_inf_trigger = '1' and in_except(63) = '1' then
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out_neg_inf <= '1';
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else
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out_neg_inf <= '0';
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end if;
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if rmode = "00" then
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round_nearest <= '1';
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else
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round_nearest <= '0';
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end if;
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if rmode = "01" then
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round_to_zero <= '1';
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else
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round_to_zero <= '0';
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end if;
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if rmode = "10" then
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round_to_pos_inf <= '1';
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else
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round_to_pos_inf <= '0';
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end if;
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if rmode = "11" then
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round_to_neg_inf <= '1';
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else
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round_to_neg_inf <= '0';
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end if;
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if (out_pos_inf = '1' and round_to_neg_inf = '1') or
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(out_neg_inf = '1' and round_to_pos_inf = '1') or
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(out_inf_trigger = '1' and round_to_zero = '1') then
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inf_round_down_trigger <= '1';
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else
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inf_round_down_trigger <= '0';
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end if;
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if multiply = '1' and opa_et_zero = '0' and opb_et_zero = '0' and
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in_et_zero = '1' then
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mul_uf <= '1';
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else
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mul_uf <= '0';
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end if;
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if divide = '1' and opa_et_zero = '0' and in_et_zero = '1' then
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div_uf <= '1';
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else
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div_uf <= '0';
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end if;
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if div_by_inf = '1' or mul_uf = '1' or div_uf = '1' then
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underflow_trigger <= '1';
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else
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underflow_trigger <= '0';
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end if;
|
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if SNaN_input = '1' or addsub_inf_invalid = '1' or mul_0_by_inf = '1' or
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div_0_by_0 = '1' or div_inf_by_inf = '1' then
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|
invalid_trigger <= '1';
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else
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|
invalid_trigger <= '0';
|
|
end if;
|
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if div_by_inf = '1' or mul_uf = '1' or div_uf = '1' then
|
|
underflow_trigger <= '1';
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else
|
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underflow_trigger <= '0';
|
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end if;
|
|
if out_inf_trigger = '1' and NaN_input = '0' then
|
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overflow_trigger <= '1';
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|
else
|
|
overflow_trigger <= '0';
|
|
end if;
|
|
if (or_reduce(mantissa_in(1 downto 0)) = '1' or out_inf_trigger = '1' or
|
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underflow_trigger = '1') and NaN_input = '0' then
|
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inexact_trigger <= '1';
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else
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inexact_trigger <= '0';
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|
end if;
|
|
if (invalid_trigger = '1' or overflow_trigger = '1' or
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underflow_trigger = '1' or inexact_trigger = '1') then
|
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except_trigger <= '1';
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|
else
|
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except_trigger <= '0';
|
|
end if;
|
|
if (invalid_trigger = '1' or overflow_trigger = '1' or
|
|
underflow_trigger = '1' or inexact_trigger = '1') then
|
|
except_trigger <= '1';
|
|
else
|
|
except_trigger <= '0';
|
|
end if;
|
|
if (except_trigger = '1' or out_inf_trigger = '1' or
|
|
NaN_input = '1') then
|
|
enable_trigger <= '1';
|
|
else
|
|
enable_trigger <= '0';
|
|
end if;
|
|
if (NaN_input = '1' or invalid_trigger = '1') then
|
|
NaN_out_trigger <= '1';
|
|
else
|
|
NaN_out_trigger <= '0';
|
|
end if;
|
|
if (invalid_trigger = '1' and SNaN_input = '0') then
|
|
SNaN_trigger <= '1';
|
|
else
|
|
SNaN_trigger <= '0';
|
|
end if;
|
|
if a_NaN = '1' then
|
|
NaN_output_0 <= exp_2047 & '1' & opa(50 downto 0);
|
|
else
|
|
NaN_output_0 <= exp_2047 & '1' & opb(50 downto 0);
|
|
end if;
|
|
if SNaN_trigger = '1' then
|
|
NaN_output <= exp_2047 & "01" & opa(49 downto 0);
|
|
else
|
|
NaN_output <= NaN_output_0;
|
|
end if;
|
|
inf_round_down <= exp_2046 & mantissa_max;
|
|
if inf_round_down_trigger = '1' then
|
|
out_inf <= inf_round_down;
|
|
else
|
|
out_inf <= exp_2047 & "0000000000000000000000000000000000000000000000000000";
|
|
end if;
|
|
if underflow_trigger = '1' then
|
|
out_0 <= in_except(63) & "000000000000000000000000000000000000000000000000000000000000000";
|
|
else
|
|
out_0 <= in_except;
|
|
end if;
|
|
if out_inf_trigger = '1' then
|
|
out_1 <= in_except(63) & out_inf;
|
|
else
|
|
out_1 <= out_0;
|
|
end if;
|
|
if NaN_out_trigger = '1' then
|
|
out_2 <= in_except(63) & NaN_output;
|
|
else
|
|
out_2 <= out_1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
process
|
|
begin
|
|
wait until clk'event and clk = '1';
|
|
if (rst = '1') then
|
|
ex_enable <= '0';
|
|
underflow <= '0';
|
|
overflow <= '0';
|
|
inexact <= '0';
|
|
exception <= '0';
|
|
invalid <= '0';
|
|
out_fp <= (others =>'0');
|
|
elsif (enable = '1') then
|
|
ex_enable <= enable_trigger;
|
|
underflow <= underflow_trigger;
|
|
overflow <= overflow_trigger;
|
|
inexact <= inexact_trigger;
|
|
exception <= except_trigger;
|
|
invalid <= invalid_trigger;
|
|
out_fp <= out_2;
|
|
end if;
|
|
end process;
|
|
end rtl;
|
|
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No newline at end of file
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|
