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---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.fpupack.all;
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ENTITY fpu_mul IS
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PORT(
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clk : IN std_logic;
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rst : IN std_logic;
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enable : IN std_logic;
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opa : IN std_logic_vector (63 DOWNTO 0);
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opb : IN std_logic_vector (63 DOWNTO 0);
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sign : OUT std_logic;
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product_7 : OUT std_logic_vector (55 DOWNTO 0);
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exponent_5 : OUT std_logic_vector (11 DOWNTO 0)
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);
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END fpu_mul;
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architecture rtl of fpu_mul is
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signal product_shift : std_logic_vector(5 downto 0);
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signal product_shift_2 : std_logic_vector(5 downto 0);
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signal mantissa_a : std_logic_vector(51 downto 0);
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signal mantissa_b : std_logic_vector(51 downto 0);
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signal exponent_a : std_logic_vector(11 downto 0);
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signal exponent_b : std_logic_vector(11 downto 0);
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signal a_is_norm : std_logic;
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signal b_is_norm : std_logic;
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signal a_is_zero : std_logic;
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signal b_is_zero : std_logic;
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signal in_zero : std_logic;
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signal exponent_terms : std_logic_vector(11 downto 0);
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signal exponent_gt_expoffset : std_logic;
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signal exponent_under : std_logic_vector(11 downto 0);
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signal exponent_1 : std_logic_vector(11 downto 0);
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signal exponent : std_logic_vector(11 downto 0);
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signal exponent_2 : std_logic_vector(11 downto 0);
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signal exponent_gt_prodshift : std_logic;
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signal exponent_3 : std_logic_vector(11 downto 0);
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signal exponent_4 : std_logic_vector(11 downto 0);
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signal exponent_et_zero : std_logic;
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signal mul_a : std_logic_vector(52 downto 0);
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signal mul_b : std_logic_vector(52 downto 0);
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signal product_a : std_logic_vector(40 downto 0);
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signal product_b : std_logic_vector(40 downto 0);
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signal product_c : std_logic_vector(40 downto 0);
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signal product_d : std_logic_vector(25 downto 0);
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signal product_e : std_logic_vector(33 downto 0);
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signal product_f : std_logic_vector(33 downto 0);
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signal product_g : std_logic_vector(35 downto 0);
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signal product_h : std_logic_vector(28 downto 0);
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signal product_i : std_logic_vector(28 downto 0);
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signal product_j : std_logic_vector(30 downto 0);
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signal sum_0 : std_logic_vector(41 downto 0);
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signal sum_1 : std_logic_vector(35 downto 0);
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signal sum_2 : std_logic_vector(41 downto 0);
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signal sum_3 : std_logic_vector(35 downto 0);
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signal sum_4 : std_logic_vector(36 downto 0);
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signal sum_5 : std_logic_vector(27 downto 0);
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signal sum_6 : std_logic_vector(29 downto 0);
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signal sum_7 : std_logic_vector(36 downto 0);
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signal sum_8 : std_logic_vector(30 downto 0);
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signal product : std_logic_vector(105 downto 0);
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signal product_1 : std_logic_vector(105 downto 0);
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signal product_2 : std_logic_vector(105 downto 0);
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signal product_3 : std_logic_vector(105 downto 0);
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signal product_4 : std_logic_vector(105 downto 0);
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signal product_5 : std_logic_vector(105 downto 0);
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signal product_6 : std_logic_vector(105 downto 0);
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signal product_lsb : std_logic;
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begin
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product_7 <= '0' & product_6(105 downto 52) & product_lsb;
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exponent <= "000000000000";
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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sign <= '0';
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mantissa_a <= (others =>'0');
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mantissa_b <= (others =>'0');
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exponent_a <= (others =>'0');
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exponent_b <= (others =>'0');
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a_is_norm <= '0';
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b_is_norm <= '0';
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a_is_zero <= '0';
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b_is_zero <= '0';
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in_zero <= '0';
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exponent_terms <= (others =>'0');
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exponent_gt_expoffset <= '0';
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exponent_under <= (others =>'0');
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exponent_1 <= (others =>'0');
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exponent_2 <= (others =>'0');
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exponent_gt_prodshift <= '0';
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exponent_3 <= (others =>'0');
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exponent_4 <= (others =>'0');
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exponent_et_zero <= '0';
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mul_a <= (others =>'0');
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mul_b <= (others =>'0');
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product_a <= (others =>'0');
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product_b <= (others =>'0');
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product_c <= (others =>'0');
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product_d <= (others =>'0');
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product_e <= (others =>'0');
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product_f <= (others =>'0');
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product_g <= (others =>'0');
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product_h <= (others =>'0');
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product_i <= (others =>'0');
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product_j <= (others =>'0');
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sum_0 <= (others =>'0');
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sum_1 <= (others =>'0');
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sum_2 <= (others =>'0');
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sum_3 <= (others =>'0');
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sum_4 <= (others =>'0');
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sum_5 <= (others =>'0');
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sum_6 <= (others =>'0');
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sum_7 <= (others =>'0');
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sum_8 <= (others =>'0');
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product <= (others =>'0');
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product_1 <= (others =>'0');
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product_2 <= (others =>'0');
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product_3 <= (others =>'0');
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product_4 <= (others =>'0');
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product_5 <= (others =>'0');
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product_6 <= (others =>'0');
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product_lsb <= '0';
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exponent_5 <= (others =>'0');
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product_shift <= (others =>'0');
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product_shift_2 <= (others =>'0');
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elsif (enable = '1') then
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sign <= opa(63) xor opb(63);
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exponent_a <= '0' & opa(62 downto 52);
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exponent_b <= '0' & opb(62 downto 52);
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mantissa_a <= opa(51 downto 0);
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mantissa_b <= opb(51 downto 0);
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a_is_norm <= or_reduce(exponent_a);
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b_is_norm <= or_reduce(exponent_b);
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a_is_zero <= not or_reduce(opa(62 downto 0));
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b_is_zero <= not or_reduce(opb(62 downto 0));
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in_zero <= a_is_zero or b_is_zero;
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exponent_terms <= exponent_a + exponent_b + ( "0000000000" & not a_is_norm) +
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("0000000000" & not b_is_norm);
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if (exponent_terms > "001111111101") then
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exponent_gt_expoffset <= '1';
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else
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exponent_gt_expoffset <= '0';
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end if;
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exponent_under <= "001111111110" - exponent_terms;
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exponent_1 <= exponent_terms - "001111111110";
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if (exponent_gt_expoffset = '1') then
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exponent_2 <= exponent_1;
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else
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exponent_2 <= exponent;
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end if;
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if (exponent_2 > product_shift_2) then
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exponent_gt_prodshift <= '1';
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else
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exponent_gt_prodshift <= '0';
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end if;
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exponent_3 <= exponent_2 - product_shift_2;
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if (exponent_gt_prodshift = '1') then
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exponent_4 <= exponent_3;
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else
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exponent_4 <= exponent;
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end if;
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if (exponent_4 = "000000000000") then
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exponent_et_zero <= '1';
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else
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exponent_et_zero <= '0';
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end if;
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mul_a <= a_is_norm & mantissa_a;
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mul_b <= b_is_norm & mantissa_b;
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product_a <= mul_a(23 downto 0) * mul_b(16 downto 0);
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product_b <= mul_a(23 downto 0) * mul_b(33 downto 17);
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product_c <= mul_a(23 downto 0) * mul_b(50 downto 34);
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product_d <= mul_a(23 downto 0) * mul_b(52 downto 51);
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product_e <= mul_a(40 downto 24) * mul_b(16 downto 0);
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product_f <= mul_a(40 downto 24) * mul_b(33 downto 17);
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product_g <= mul_a(40 downto 24) * mul_b(52 downto 34);
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product_h <= mul_a(52 downto 41) * mul_b(16 downto 0);
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product_i <= mul_a(52 downto 41) * mul_b(33 downto 17);
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product_j <= mul_a(52 downto 41) * mul_b(52 downto 34);
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sum_0 <= product_a(40 downto 17) + ( '0' & product_b);
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sum_1 <= ('0' & sum_0(41 downto 7)) + product_e;
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sum_2 <= sum_1(35 downto 10) + ('0' & product_c);
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sum_3 <= ( '0' & sum_2(41 downto 7)) + product_h;
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sum_4 <= ( '0' & sum_3) + product_f;
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sum_5 <= ('0' & sum_4(36 downto 10)) + product_d;
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sum_6 <= sum_5(27 downto 7) + ('0' & product_i);
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sum_7 <= sum_6 + ('0' & product_g);
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sum_8 <= sum_7(36 downto 17) + product_j;
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product <= sum_8 & sum_7(16 downto 0) & sum_5(6 downto 0) & sum_4(9 downto 0) & sum_2(6 downto 0) &
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sum_1(9 downto 0) & sum_0(6 downto 0) & product_a(16 downto 0);
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product_1 <= shr(product, exponent_under);
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if (exponent_gt_prodshift = '1') then
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product_5 <= product_3;
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else
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product_5 <= product_4;
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end if;
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if (exponent_gt_expoffset = '1') then
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product_2 <= product;
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else
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product_2 <= product_1;
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end if;
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product_3 <= shl(product_2, product_shift_2);
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product_4 <= shl(product_2, exponent_2);
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if (exponent_gt_prodshift = '1') then
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product_5 <= product_3;
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else
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product_5 <= product_4;
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end if;
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if (exponent_et_zero = '1') then
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product_6 <= shr(product_5, conv_std_logic_vector('1', 106));
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else
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product_6 <= product_5;
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end if;
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product_lsb <= or_reduce(product_6(51 downto 0));
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if (in_zero = '1') then
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exponent_5 <= "000000000000";
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else
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exponent_5 <= exponent_4;
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end if;
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product_shift <= count_zeros_mul(product(105 downto 0));
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product_shift_2 <= product_shift;
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end if;
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end process;
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end rtl;
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