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---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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ENTITY fpu_round IS
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PORT(
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clk, rst, enable : IN std_logic;
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round_mode : IN std_logic_vector (1 DOWNTO 0);
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sign_term : IN std_logic;
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mantissa_term : IN std_logic_vector (55 DOWNTO 0);
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exponent_term : IN std_logic_vector (11 DOWNTO 0);
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round_out : OUT std_logic_vector (63 DOWNTO 0);
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exponent_final : OUT std_logic_vector (11 DOWNTO 0)
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);
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END fpu_round;
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architecture rtl of fpu_round is
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signal rounding_amount : std_logic_vector(55 downto 0);
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signal round_nearest : std_logic;
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signal round_to_zero : std_logic;
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signal round_to_pos_inf : std_logic;
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signal round_to_neg_inf : std_logic;
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signal round_nearest_trigger : std_logic;
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signal round_to_pos_inf_trigger : std_logic;
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signal round_to_neg_inf_trigger : std_logic;
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signal round_trigger : std_logic;
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signal sum_round : std_logic_vector(55 downto 0);
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signal sum_round_overflow : std_logic;
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-- will be 0 if no carry, 1 if overflow from the rounding unit
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-- overflow from rounding is extremely rare, but possible
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signal sum_round_2 : std_logic_vector(55 downto 0);
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signal exponent_round : std_logic_vector(11 downto 0);
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signal exponent_final_2 : std_logic_vector(11 downto 0);
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signal sum_final : std_logic_vector(55 downto 0);
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begin
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rounding_amount <= "00000000000000000000000000000000000000000000000000000100";
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round_nearest <= '1' when (round_mode = "00") else '0';
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round_to_zero <= '1' when (round_mode = "01") else '0';
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round_to_pos_inf <= '1' when (round_mode = "10") else '0';
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round_to_neg_inf <= '1' when (round_mode = "11") else '0';
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round_nearest_trigger <= '1' when round_nearest = '1' and mantissa_term(1) = '1'
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else '0';
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round_to_pos_inf_trigger <= '1' when sign_term = '0' and
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or_reduce(mantissa_term(1 downto 0)) = '1' else '0';
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round_to_neg_inf_trigger <= '1' when sign_term = '1' and
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or_reduce(mantissa_term(1 downto 0)) = '1' else '0';
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round_trigger <= '1' when ( round_nearest = '1' and round_nearest_trigger = '1')
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or (round_to_pos_inf = '1' and round_to_pos_inf_trigger = '1')
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or (round_to_neg_inf = '1' and round_to_neg_inf_trigger = '1')
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else '0';
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sum_round_overflow <= sum_round(55);
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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sum_round <= (others =>'0');
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sum_round_2 <= (others =>'0');
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exponent_round <= (others =>'0');
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sum_final <= (others =>'0');
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exponent_final <= (others =>'0');
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exponent_final_2 <= (others =>'0');
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round_out <= (others =>'0');
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else
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sum_round <= rounding_amount + mantissa_term;
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if sum_round_overflow = '1' then
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sum_round_2 <= shr(sum_round, conv_std_logic_vector('1', 56));
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exponent_round <= exponent_term + "000000000001";
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else
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sum_round_2 <= sum_round;
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exponent_round <= exponent_term;
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end if;
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if round_trigger = '1' then
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sum_final <= sum_round_2;
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exponent_final_2 <= exponent_round;
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else
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sum_final <= mantissa_term;
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exponent_final_2 <= exponent_term;
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end if;
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exponent_final <= exponent_final_2;
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round_out <= sign_term & exponent_final_2(10 downto 0) & sum_final(53 downto 2);
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end if;
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end process;
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end rtl;
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