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Line 40... |
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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LIBRARY HAVOC;
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ARCHITECTURE single_cycle OF FPmul IS
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ARCHITECTURE single_cycle OF FPmul IS
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-- Architecture declarations
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-- Architecture declarations
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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Line 130... |
);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
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FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
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FOR ALL : FPround USE ENTITY HAVOC.FPround;
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FOR ALL : FPround USE ENTITY work.FPround;
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FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
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FOR ALL : PackFP USE ENTITY work.PackFP;
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FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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Line 230... |
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-- HDL Embedded Text Block 6 eb6
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-- HDL Embedded Text Block 6 eb6
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-- eb6 6
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-- eb6 6
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PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
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PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
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BEGIN
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BEGIN
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IF (EXP_out(7)='1' AND A_EXP(7)='0' AND B_EXP(7)='0') OR
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IF ( EXP_out(7)='1' AND
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(SIG_out_norm2(26 DOWNTO 3)="000000000000000000000000") THEN
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( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
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(B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
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(SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
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-- Underflow or zero significand
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-- Underflow or zero significand
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SIG_isZ <= '1';
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SIG_isZ <= '1';
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ELSE
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ELSE
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SIG_isZ <= '0';
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SIG_isZ <= '0';
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END IF;
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END IF;
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