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`include "defines.v"
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`include "defines.v"
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module divider(in, out, P, reset);
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module divider(in, out, N, reset);
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input in;
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input in; // input clock
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input [`SIZE-1:0] P;
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input [`SIZE-1:0] N; // the number to be divided by
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input reset;
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input reset; // asynchronous reset
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output out;
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output out; // divided output clock
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wire out_odd;
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wire out_odd; // output of odd divider
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wire out_even;
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wire out_even; // output of even divider
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wire not_zero;
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wire not_zero; // signal to find divide by 0 case
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wire enable_even;
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wire enable_even; // enable of even divider
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wire enable_odd;
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wire enable_odd; // enable of odd divider
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assign not_zero = | P[`SIZE-1:1];
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assign not_zero = | N[`SIZE-1:1];
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assign out = (out_odd & P[0] & not_zero) | (out_even & !P[0]);
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assign out = (out_odd & N[0] & not_zero) | (out_even & !N[0]);
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//assign out = out_odd | out_even;
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//assign out = out_odd | out_even;
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assign enable_odd = P[0] & not_zero;
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assign enable_odd = N[0] & not_zero;
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assign enable_even = !P[0];
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assign enable_even = !N[0];
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even even_0(in, out_even, P, reset, not_zero, enable_even);
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// Even divider
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odd odd_0(in, out_odd, P, reset, enable_odd);
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even even_0(in, out_even, N, reset, not_zero, enable_even);
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// Odd divider
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odd odd_0(in, out_odd, N, reset, enable_odd);
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endmodule //divider
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endmodule //divider
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