Subversion Repositories freq_div

module divider(in, out, P, reset);

module divider(in, out, N, reset);

        input in;

        input in;                               // input clock

        input [`SIZE-1:0] P;

        input [`SIZE-1:0] N;     // the number to be divided by

        input reset;

        input reset;                    // asynchronous reset

        output out;

        output out;                             // divided output clock

        wire out_odd;

        wire out_odd;                   // output of odd divider

        wire out_even;

        wire out_even;                  // output of even divider

        wire not_zero;

        wire not_zero;                  // signal to find divide by 0 case

        wire enable_even;

        wire enable_even;               // enable of even divider

        wire enable_odd;

        wire enable_odd;                // enable of odd divider

        assign not_zero = | P[`SIZE-1:1];

        assign not_zero = | N[`SIZE-1:1];

        assign out = (out_odd & P[0] & not_zero) | (out_even & !P[0]);

        assign out = (out_odd & N[0] & not_zero) | (out_even & !N[0]);

        assign enable_odd = P[0] & not_zero;

        assign enable_odd = N[0] & not_zero;

        assign enable_even = !P[0];

        assign enable_even = !N[0];

        even even_0(in, out_even, P, reset, not_zero, enable_even);

        // Even divider

        odd odd_0(in, out_odd, P, reset, enable_odd);

        even even_0(in, out_even, N, reset, not_zero, enable_even);