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`include "defines.v"
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`include "defines.v"
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module even(clk, out, P, reset, not_zero, enable);
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module even(clk, out, N, reset, not_zero, enable);
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input clk;
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input clk; // fast input clock
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output out;
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output out; // slower divided clock
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input [`SIZE-1:0] P;
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input [`SIZE-1:0] N; // divide by factor 'N'
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input reset;
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input reset; // asynchronous reset
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input not_zero;
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input not_zero; // if !not_zero divide by 1
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input enable;
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input enable; // enable the even divider
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reg [`SIZE-1:0] counter;
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reg [`SIZE-1:0] counter;
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reg out_counter;
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reg out_counter;
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wire [`SIZE-1:0] div_2;
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wire [`SIZE-1:0] div_2;
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// if N=0 just output the clock, otherwise, divide it.
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assign out = (clk & !not_zero) | (out_counter & not_zero);
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assign out = (clk & !not_zero) | (out_counter & not_zero);
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assign div_2 = {1'b0, P[`SIZE-1:1]};
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assign div_2 = {1'b0, N[`SIZE-1:1]};
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// simple flip-flop even divider
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always @(posedge reset or posedge clk)
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always @(posedge reset or posedge clk)
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begin
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begin
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if(reset)
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if(reset) // asynch. reset
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begin
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begin
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counter <= 1;
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counter <= 1;
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out_counter <= 1;
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out_counter <= 1;
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end
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end
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else if(enable)
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else if(enable) // only use switching power if enabled
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begin
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if(counter == 1)
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begin
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begin
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if(counter == 1) // divide after counter has reached bottom
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begin // of interval 'N' which will be value '1'
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counter <= div_2;
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counter <= div_2;
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out_counter <= ~out_counter;
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out_counter <= ~out_counter;
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end
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end
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else
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else
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begin
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begin // decrement the counter and wait
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counter <= counter-1;
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counter <= counter-1; // to start next trasition.
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end
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end
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end
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end
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end
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end
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endmodule //even
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endmodule //even
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