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https://opencores.org/ocsvn/freq_div/freq_div/trunk
[/] [freq_div/] [trunk/] [rtl/] [odd.v] - Diff between revs 4 and 5
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| Rev 4 |
Rev 5 |
| Line 34... |
Line 34... |
counter <= N;
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counter <= N;
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out_counter <= ~out_counter;
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out_counter <= ~out_counter;
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end
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end
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else
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else
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begin
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begin
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counter <= counter-1;
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counter <= counter - 1'b1;
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end
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end
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end
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end
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end
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end
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reg [`SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
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reg [`SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
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wire [`SIZE:0] interm_3; // from the positive edge counter in order to
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wire [`SIZE:0] interm_3; // from the positive edge counter in order to
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assign interm_3 = {1'b0,N} + 3; // guarante 50% duty cycle.
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assign interm_3 = {1'b0,N} + 2'b11; // guarante 50% duty cycle.
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// counter driven by negative edge of clock.
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// counter driven by negative edge of clock.
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always @(negedge clk)
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always @(negedge clk)
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begin
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begin
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if(reset | rst_pulse) // reset the counter at system reset
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if(reset | rst_pulse) // reset the counter at system reset
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| Line 61... |
Line 61... |
counter2 <= N;
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counter2 <= N;
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out_counter2 <= ~out_counter2;
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out_counter2 <= ~out_counter2;
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end
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end
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else
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else
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begin
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begin
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counter2 <= counter2-1;
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counter2 <= counter2 - 1'b1;
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end
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end
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end
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end
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else if(enable)
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else if(enable)
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begin
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begin
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initial_begin <= initial_begin - 1;
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initial_begin <= initial_begin - 1'b1;
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end
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end
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end
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end
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//
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//
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// reset pulse generator:
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// reset pulse generator:
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| Line 98... |
Line 98... |
else
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else
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begin
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begin
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rst_pulse <= 0;
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rst_pulse <= 0;
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end
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end
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end
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end
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end
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always @(posedge clk)
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begin
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old_N <= N; // always save the old N value to guarante reset from
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old_N <= N; // always save the old N value to guarante reset from
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end // an even-to-odd transition.
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end // an even-to-odd transition.
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endmodule //odd
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endmodule //odd
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No newline at end of file
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