| Line 90... |
Line 90... |
data_io <= out_buff when we = '1' else
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data_io <= out_buff when we = '1' else
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"ZZZZZZZZ" when we = '0' else
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"ZZZZZZZZ" when we = '0' else
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"XXXXXXXX";
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"XXXXXXXX";
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in_buff <= data_io;
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in_buff <= data_io;
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|
|
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busy <= '1' when c_state /= IDLE else
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'0';
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|
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process(clk, reset, nrxf, ntxe, nce)
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-- Reset the FT245R chip on powerup.
|
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nrst <= '0' when c_state = INIT else
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'1';
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|
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nrd <= '0' when c_state = READ_BYTE or c_state = READ_BYTE1 or
|
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(c_state = DO_DELAY and (n_state = READ_BYTE1 or n_state = READ_BYTE2)) else
|
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'1';
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|
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nwr <= '1' when (c_state = WRITE_BYTE and ntxe = '0') or (c_state = DO_DELAY and n_state = WRITE_BYTE1) else
|
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'0';
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|
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we <= '1' when (c_state = WRITE_BYTE and ntxe = '0') or c_state = WRITE_BYTE1 or (c_state = DO_DELAY and (n_state = WRITE_BYTE1 or n_state = WRITE_BYTE2)) else
|
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'0';
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|
|
process(clk, reset, nrxf, ntxe, nce, data_available, fetch_next_byte, do_write)
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begin
|
begin
|
if(reset = '0')then
|
if(reset = '0')then
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c_state <= INIT;
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c_state <= INIT;
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elsif(rising_edge(clk) and nce = '0')then
|
elsif(rising_edge(clk) and nce = '0')then
|
|
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| Line 103... |
Line 119... |
-- The module enters this state on powerup or when 'reset' is low.
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-- The module enters this state on powerup or when 'reset' is low.
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when INIT =>
|
when INIT =>
|
delay_cnt <= 0;
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delay_cnt <= 0;
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current_delay <= 0;
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current_delay <= 0;
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c_state <= IDLE;
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c_state <= IDLE;
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nrst <= '0'; -- Reset FT245RL on init
|
|
|
|
-- This is the "main loop"
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-- This is the "main loop"
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when IDLE =>
|
when IDLE =>
|
nrst <= '1';
|
|
|
|
-- If this condition is true, we may safely read another byte from FT245RL's FIFO
|
-- If this condition is true, we may safely read another byte from FT245RL's FIFO
|
if(nrxf = '0' and data_available = '0')then
|
if(nrxf = '0' and data_available = '0')then
|
c_state <= READ_BYTE;
|
c_state <= READ_BYTE;
|
|
|
-- We have to clear 'data_available' when the client module is requesting a new byte
|
-- We have to clear 'data_available' when the client module is requesting a new byte
|
elsif(fetch_next_byte = '1')then
|
elsif(fetch_next_byte = '1')then
|
data_available <= '0';
|
data_available <= '0';
|
c_state <= IDLE;
|
c_state <= READ_BYTE;
|
|
|
-- Well, here we simply write a byte to FT245RL's data bus
|
-- Well, here we simply write a byte to FT245RL's data bus
|
elsif(do_write = '1')then
|
elsif(do_write = '1')then
|
c_state <= WRITE_BYTE;
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c_state <= WRITE_BYTE;
|
end if;
|
end if;
|
|
|
|
|
-- Read one byte from the device
|
-- Read one byte from the device
|
when READ_BYTE =>
|
when READ_BYTE =>
|
busy <= '1';
|
|
nrd <= '0';
|
|
current_delay <= t3_delay;
|
current_delay <= t3_delay;
|
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= READ_BYTE1;
|
n_state <= READ_BYTE1;
|
|
|
when READ_BYTE1 =>
|
when READ_BYTE1 =>
|
| Line 139... |
Line 150... |
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= READ_BYTE2;
|
n_state <= READ_BYTE2;
|
|
|
when READ_BYTE2 =>
|
when READ_BYTE2 =>
|
data_out <= in_buff;
|
data_out <= in_buff;
|
nrd <= '1';
|
|
current_delay <= t5_delay;
|
current_delay <= t5_delay;
|
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= READ_BYTE3;
|
n_state <= READ_BYTE3;
|
|
|
when READ_BYTE3 =>
|
when READ_BYTE3 =>
|
current_delay <= t2_delay;
|
current_delay <= t2_delay;
|
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= IDLE;
|
n_state <= IDLE;
|
data_available <= '1';
|
data_available <= '1';
|
busy <= '0';
|
|
|
|
-- Write one byte to the device
|
-- Write one byte to the device
|
when WRITE_BYTE =>
|
when WRITE_BYTE =>
|
busy <= '1';
|
|
if(ntxe = '0')then
|
if(ntxe = '0')then
|
nwr <= '1';
|
|
we <= '1';
|
|
current_delay<= t7_delay;
|
current_delay<= t7_delay;
|
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= WRITE_BYTE1;
|
n_state <= WRITE_BYTE1;
|
out_buff <= data_in;
|
out_buff <= data_in;
|
else
|
else
|
c_state <= WRITE_BYTE;
|
c_state <= WRITE_BYTE;
|
end if;
|
end if;
|
|
|
when WRITE_BYTE1 =>
|
when WRITE_BYTE1 =>
|
nwr <= '0';
|
|
current_delay <= t11_delay;
|
current_delay <= t11_delay;
|
c_state <= DO_DELAY;
|
c_state <= DO_DELAY;
|
n_state <= WRITE_BYTE2;
|
n_state <= WRITE_BYTE2;
|
|
|
when WRITE_BYTE2 =>
|
when WRITE_BYTE2 =>
|
we <= '0';
|
|
current_delay <= t12_delay;
|
current_delay <= t12_delay;
|
c_state <=DO_DELAY;
|
c_state <=DO_DELAY;
|
n_state <= WRITE_BYTE3;
|
n_state <= WRITE_BYTE3;
|
|
|
when WRITE_BYTE3 =>
|
when WRITE_BYTE3 =>
|
busy <= '0';
|
|
c_state <= IDLE;
|
c_state <= IDLE;
|
|
|
when DO_DELAY =>
|
when DO_DELAY =>
|
if(delay_cnt < current_delay)then
|
if(delay_cnt < current_delay)then
|
delay_cnt <= delay_cnt + 1;
|
delay_cnt <= delay_cnt + 1;
|
