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// ============================================================================
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// intToPosit.sv
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// - integer to posit number converter
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// - parameterized width
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ============================================================================
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module intToPosit_tb_v;
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module intToPosit_tb_v;
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function [31:0] log2;
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function [31:0] log2;
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input reg [31:0] value;
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input reg [31:0] value;
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endfunction
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endfunction
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parameter N=32;
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parameter N=32;
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parameter E=8;
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parameter E=8;
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parameter Bs=log2(N);
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parameter Bs=log2(N);
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parameter es = 4;
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parameter es = 2;
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reg clk;
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reg clk;
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reg [5:0] cnt;
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reg [5:0] cnt;
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wire [N-1:0] out;
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wire [N-1:0] out, outi;
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reg [N-1:0] a;
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reg [N-1:0] a, a1;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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intToPosit #(.PSTWID(N), .es(es)) u2 (.i(a), .o(out));
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intToPosit #(.PSTWID(N), .es(es)) u2 (.i(a), .o(out));
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positToInt #(.PSTWID(N), .es(es)) u3 (.i(out), .o(outi));
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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$finish;
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$finish;
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end
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end
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always #5 clk=~clk;
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always #5 clk=~clk;
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always @(posedge clk) begin
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always @(posedge clk) begin
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a = $urandom();
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a <= $urandom();
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cnt = cnt + 1;
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cnt <= cnt + 1;
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case (cnt)
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case (cnt)
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1: a = 8192;
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1: a <= 8192;
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2: a = 10;
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2: a <= 10;
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3: a = -1;
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3: a <= -1;
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4: a = -10;
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4: a <= -10;
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default: a = $urandom();
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5: a <= 100;
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default: a <= $urandom();
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endcase
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endcase
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end
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end
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integer outfile;
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integer outfile;
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initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/intToPosit_tvo32.txt", "wb");
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initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/intToPosit_tvo32.txt", "wb");
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always @(negedge clk) begin
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always @(posedge clk) begin
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$fwrite(outfile, "%d\t%h\n",a,out);
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$fwrite(outfile, "%d\t%h\t%d\n",a,out,outi);
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end
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end
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endmodule
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endmodule
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