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Line 53... |
parameter E=8;
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parameter E=8;
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parameter Bs=log2(N);
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parameter Bs=log2(N);
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parameter es = 2;
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parameter es = 2;
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reg clk;
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reg clk;
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reg [5:0] cnt;
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reg [15:0] cnt;
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wire [N-1:0] out, outi;
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wire [N-1:0] out, outi;
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reg [N-1:0] a, a1;
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reg [N-1:0] a, a1;
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reg [31:0] fa;
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wire [31:0] f2po;
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fpToPosit #(.FPWID(32)) ufp1 (.i(fa), .o(f2po));
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wire [63:0] double = {fa[31], fa[30], {3{~fa[30]}}, fa[29:23], fa[22:0], {29{1'b0}}};
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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intToPosit #(.PSTWID(N), .es(es)) u2 (.i(a), .o(out));
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intToPosit #(.PSTWID(N), .es(es)) u2 (.i(a), .o(out));
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positToInt #(.PSTWID(N), .es(es)) u3 (.i(out), .o(outi));
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positToInt #(.PSTWID(N), .es(es)) u3 (.i(f2po), .o(outi));
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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Line 88... |
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always #5 clk=~clk;
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always #5 clk=~clk;
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always @(posedge clk) begin
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always @(posedge clk) begin
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a <= $urandom();
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a <= $urandom();
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cnt <= cnt + 1;
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cnt <= cnt + 1;
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if (cnt > 1000) begin
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fa <= $urandom();
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end
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else
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case (cnt)
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case (cnt)
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1: a <= 8192;
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2: fa <= 32'h3f000001; // 0.5 + 1ulp
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2: a <= 10;
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3: fa <= 32'h3EFFFFFF; // 0.4999...
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3: a <= -1;
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4: a <= 32'h17cf4600;
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4: a <= -10;
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5: a <= 10;
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5: a <= 100;
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6: a <= -1;
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7: a <= -10;
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8: a <= 100;
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default: a <= $urandom();
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default: a <= $urandom();
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endcase
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endcase
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end
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end
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integer outfile;
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integer outfile;
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initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/intToPosit_tvo32.txt", "wb");
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initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/intToPosit_tvo32.txt", "wb");
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always @(posedge clk) begin
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always @(posedge clk) begin
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$fwrite(outfile, "%d\t%h\t%d\n",a,out,outi);
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$fwrite(outfile, "%h\t%d\t%h\t%d\t%e\n",f2po,a,out,outi,$bitstoreal(double));
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end
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end
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endmodule
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endmodule
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