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[/] [ft816float/] [trunk/] [posit_test_bench/] [positAddsub_tb.v] - Diff between revs 36 and 44

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Rev 36	Rev 44
Line 8...	Line 8...
`for (log2=0; value>0; log2=log2+1)`	`for (log2=0; value>0; log2=log2+1)`
`value = value>>1;`	`value = value>>1;`
`end`	`end`
`endfunction`	`endfunction`

`parameter N=52;`	`parameter N=32;`
`parameter E=8;`	`parameter E=8;`
`parameter Bs=log2(N);`	`parameter Bs=log2(N);`
`parameter es = 4;`	`parameter es = 2;`

`reg [N-1:0] in;`	`reg [N-1:0] in;`
`reg clk;`	`reg clk;`
`reg [5:0] cnt;`	`reg [5:0] cnt;`

Line 27...	Line 27...

`// Instantiate the Unit Under Test (UUT)`	`// Instantiate the Unit Under Test (UUT)`

`intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));`	`intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));`
`intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));`	`intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));`
`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u2`	`/*`
`(`	`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u2`
`.i(a),`	`(`
`.o(fa)`	`.i(a),`
`);`	`.o(fa)`
	`);`
`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u3`
`(`	`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u3`
`.i(b),`	`(`
`.o(fb)`	`.i(b),`
`);`	`.o(fb)`
	`);`
`positAddsub #(.PSTWID(N), .es(es)) uadd1 (1'b0,a,b,psum);`	`*/`
`fpAddsub #(.FPWID(N)) uadd2 (clk,1'b1,3'd0,1'b0,fa,fb,fsum);`	`positAddsub #(.PSTWID(N), .es(es)) uadd1 (1'b0,a1,b1,psum);`
`posit_add #(.N(N),.es(es)) uadd3 (a, b, 1'b1, psum1);`	`//fpAddsub #(.FPWID(N)) uadd2 (clk,1'b1,3'd0,1'b0,fa,fb,fsum);`
	`posit_add #(.N(N),.es(es)) uadd3 (a1, b1, 1'b1, psum1);`
`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u4`	`/*`
`(`	`positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u4`
`.i(psum),`	`(`
`.o(out2)`	`.i(psum),`
`);`	`.o(out2)`
	`);`
	`*/`

`delay2 #(N) ud1 (.i(a), .o(ad));`	`delay2 #(N) ud1 (.i(a), .o(ad));`
`delay2 #(N) ud2 (.i(a), .o(bd));`	`delay2 #(N) ud2 (.i(a), .o(bd));`
`delay2 #(N) ud3 (.i(psum), .o(psumd));`	`delay2 #(N) ud3 (.i(psum), .o(psumd));`
`delay2 #(N) ud4 (.i(out2), .o(out2d));`	`delay2 #(N) ud4 (.i(out2), .o(out2d));`
Line 73...	Line 74...
`#325150`	`#325150`
`$fclose(outfile);`	`$fclose(outfile);`
`$finish;`	`$finish;`
`end`	`end`

	`// 23acc3ec 2d37240c 230d8602 630d8602*`
	`// 343b2e06 6c4e8633 6c5194ff 6c5194fe*`
`always #5 clk=~clk;`	`always #5 clk=~clk;`
`always @(posedge clk) begin`	`always @(posedge clk) begin`
`cnt = cnt + 1;`	`cnt = cnt + 1;`
`case(cnt)`	`case(cnt)`
`0:`	`0:`
Line 89...	Line 92...
`a1 = 0;`	`a1 = 0;`
`b1 = 10;`	`b1 = 10;`
`end`	`end`
`2:`	`2:`
`begin`	`begin`
`a1 = 10;`	`a1 = 32'h23acc3ec;`
`b1 = 10;`	`b1 = 32'h2d37240c;`
	`end`

	`3:`
	`begin`
	`a1 = 32'h343b2e06;`
	`b1 = 32'h6c4e8633;`
`end`	`end`

`default:`	`default:`
`begin`	`begin`
`a1 = $urandom();`	`a1 = $urandom();`
Line 102...	Line 111...
`end`	`end`
`endcase`	`endcase`
`end`	`end`

`integer outfile;`	`integer outfile;`
`initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/positAddsub_tvo32.txt", "wb");`	`initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/positAddsub_tvo32.txt", "wb");`
`always @(negedge clk) begin`	`always @(negedge clk) begin`
`$fwrite(outfile, "%h\t%h\t%h\t%h\n",a,b,psum,psum1);`	`$fwrite(outfile, "%h\t%h\t%h\t%h%c\n",a1,b1,psum,psum1,psum!=psum1?"*":" ");`
`end`	`end`

`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

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[/] [ft816float/] [trunk/] [posit_test_bench/] [positAddsub_tb.v] - Diff between revs 36 and 44