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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// positDivide.sv
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// div_lut.sv
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// - posit number division function
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// - divide reciprocal lookup table
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// - parameterized width
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// - 2048 entries (1 block ram)
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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module div_lut(clk, i, o);
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module div_lut(clk, ce, i, o);
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input clk;
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input clk;
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input ce;
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input [10:0] i;
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input [10:0] i;
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output reg [15:0] o;
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output reg [15:0] o;
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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case(i)
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case(i)
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11'h000: o <= 16'hFFFF;
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11'h000: o <= 16'hFFFF;
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11'h001: o <= 16'hFFE0;
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11'h001: o <= 16'hFFE0;
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11'h002: o <= 16'hFFC0;
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11'h002: o <= 16'hFFC0;
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11'h003: o <= 16'hFFA0;
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11'h003: o <= 16'hFFA0;
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