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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// fpToPosit.v
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// fpToPosit.sv
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// - floating point to posit number convertor
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// - floating point to posit number convertor
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// - can issue every clock cycle
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// - can issue every clock cycle
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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import fp::*;
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`include "fpConfig.sv"
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import posit::*;
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`include "fpTypes.sv"
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module fpToPosit(i, o);
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module fpToPosit(i, o);
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parameter FPWID = 32;
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`include "fpSize.sv"
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`include "positSize.sv"
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input [FPWID-1:0] i;
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input [FPWID-1:0] i;
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output reg [FPWID-1:0] o;
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output reg [FPWID-1:0] o;
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parameter BIAS = {1'b0,{EMSB{1'b1}}};
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parameter BIAS = {1'b0,{EMSB{1'b1}}};
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localparam N = FPWID;
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localparam N = FPWID;
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wire az;
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wire az;
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wire xainf;
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wire xainf;
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wire aInf;
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wire aInf;
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wire aNan;
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wire aNan;
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fpDecomp #(FPWID) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecomp #(.FPWID(FPWID)) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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assign sgno = sa;
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assign sgno = sa;
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wire [$clog2(FMSB+1):0] lzcnt;
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wire [$clog2(FMSB+1):0] lzcnt;
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generate begin : gCntlz
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generate begin : gCntlz
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case(FPWID)
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case(FPWID)
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16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end //1-5-10
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16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end //1-5-10
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