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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [fpToPosit.sv] - Diff between revs 36 and 48

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Rev 36 Rev 48
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      fpToPosit.v
//      fpToPosit.sv
//    - floating point to posit number convertor
//    - floating point to posit number convertor
//    - can issue every clock cycle
//    - can issue every clock cycle
//    - parameterized width
//    - parameterized width
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
 
 
`include "positConfig.sv"
import fp::*;
`include "fpConfig.sv"
import posit::*;
`include "fpTypes.sv"
 
 
 
module fpToPosit(i, o);
module fpToPosit(i, o);
parameter FPWID = 32;
 
`include "fpSize.sv"
 
`include "positSize.sv"
 
input [FPWID-1:0] i;
input [FPWID-1:0] i;
output reg [FPWID-1:0] o;
output reg [FPWID-1:0] o;
 
 
parameter BIAS = {1'b0,{EMSB{1'b1}}};
parameter BIAS = {1'b0,{EMSB{1'b1}}};
localparam N = FPWID;
localparam N = FPWID;
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wire az;
wire az;
wire xainf;
wire xainf;
wire aInf;
wire aInf;
wire aNan;
wire aNan;
 
 
fpDecomp #(FPWID) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
fpDecomp #(.FPWID(FPWID)) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
assign sgno = sa;
assign sgno = sa;
wire [$clog2(FMSB+1):0] lzcnt;
wire [$clog2(FMSB+1):0] lzcnt;
generate begin : gCntlz
generate begin : gCntlz
case(FPWID)
case(FPWID)
16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end  //1-5-10
16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end  //1-5-10

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