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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [intToPosit.sv] - Diff between revs 36 and 42

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Rev 36 Rev 42
Line 28... Line 28... 
`include "positConfig.sv"
 
`include "positConfig.sv"
 
 
 
 
 
module intToPosit(i, o);
 
module intToPosit(i, o);
 
`include "positSize.sv"
 
`include "positSize.sv"
 
localparam rs = $clog2(PSTWID-1);
 
localparam rs = $clog2(PSTWID-1);
 
localparam lzs = $clog2(PSTWID-2);
 
localparam lzs = $clog2(PSTWID-1)-1;
 
input [PSTWID-1:0] i;
 
input [PSTWID-1:0] i;
 
output [PSTWID-1:0] o;
 
output [PSTWID-1:0] o;
 
 
 
 
 
wire [PSTWID*2-1+es+3-2:0] tmp, tmp1;
 
wire [PSTWID*2-1+es+3-2:0] tmp, tmp1;
 
wire [PSTWID-2:0] ii = i[PSTWID-1] ? -i : i;
 
wire [PSTWID-2:0] ii = i[PSTWID-1] ? -i : i;

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