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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [isqrt2.v] - Diff between revs 40 and 42

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Rev 40 Rev 42
Line 122... Line 122...
assign done = state==DONE && cnt > 8'd0;
assign done = state==DONE && cnt > 8'd0;
 
 
endmodule
endmodule
 
 
 
 
module isqrt_tb();
module isqrt2_tb();
 
 
reg clk;
reg clk;
reg rst;
reg rst;
reg [31:0] a;
reg [31:0] a;
wire [63:0] o;
wire [63:0] o;
Line 163... Line 163...
                $display("i=%h o=%h", a, o);
                $display("i=%h o=%h", a, o);
        end
        end
endcase
endcase
end
end
 
 
isqrt #(32) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(ld), .a(a), .o(o), .done(done));
isqrt2 #(32) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(ld), .a(a), .o(o), .done(done));
 
 
endmodule
endmodule
 
 
 
 
 
 
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