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`include "positConfig.sv"
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`include "positConfig.sv"
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module positAddsub(op, a, b, o);
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module positAddsub(op, a, b, o);
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`include "positSize.sv"
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1)-1;
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localparam rs = $clog2(PSTWID-1);
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input op;
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input op;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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input [PSTWID-1:0] b;
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output reg [PSTWID-1:0] o;
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output reg [PSTWID-1:0] o;
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endgenerate
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endgenerate
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//positCntlz #(.PSTWID(PSTWID)) u3 (.i({|sigov,sig_sd[PSTWID-2:0]}), .o(lzcnt));
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//positCntlz #(.PSTWID(PSTWID)) u3 (.i({|sigov,sig_sd[PSTWID-2:0]}), .o(lzcnt));
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wire [PSTWID*2-1:0] sig_ls = sig_sd[PSTWID*2-1:0] << lzcnt;
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wire [PSTWID*2-1:0] sig_ls = sig_sd[PSTWID*2-1:0] << lzcnt;
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wire [rs:0] absrgm1 = rgs1 ? rgm1 : -rgm1; // rgs1 = 1 = positive
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wire [rs+1:0] absrgm1 = rgs1 ? rgm1 : -rgm1; // rgs1 = 1 = positive
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wire [es+rs+1:0] rxtmp;
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wire [es+rs+1:0] rxtmp;
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wire [es+rs+1:0] rxtmp1;
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wire [es+rs+1:0] rxtmp1;
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wire srxtmp1;
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wire srxtmp1;
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wire [es+rs:0] abs_rxtmp;
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wire [es+rs:0] abs_rxtmp;
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wire [(es==0 ? 0 : es-1):0] expo;
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wire [(es==0 ? 0 : es-1):0] expo;
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wire [rs:0] rgmo;
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wire [rs:0] rgmo;
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generate begin : gEsz
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generate begin : gEsz
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if (es > 0) begin
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if (es > 0) begin
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assign rxtmp = {absrgm1,exp1} - {{es+1{1'b0}},lzcnt-es};
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assign rxtmp = {absrgm1,exp1} + es - {{es+1{1'b0}},lzcnt};
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign srxtmp1 = rxtmp1[es+rs+1];
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assign srxtmp1 = rxtmp1[es+rs+1];
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assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
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assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
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assign expo = (srxtmp1 & |abs_rxtmp[es-1:0]) ? rxtmp1[es-1:0] : abs_rxtmp[es-1:0];
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assign expo = (srxtmp1 & |abs_rxtmp[es-1:0]) ? rxtmp1[es-1:0] : abs_rxtmp[es-1:0];
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assign rgmo = (~srxtmp1 || (srxtmp1 & |abs_rxtmp[es-1:0])) ? abs_rxtmp[es+rs:es] + 1'b1 : abs_rxtmp[es+rs:es];
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assign rgmo = (~srxtmp1 || (|abs_rxtmp[es-1:0])) ? abs_rxtmp[es+rs:es] + 1'b1 : abs_rxtmp[es+rs:es];
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end
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end
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else begin
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else begin
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assign rxtmp = absrgm1 - {{1{1'b0}},lzcnt};
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assign rxtmp = absrgm1 - {{1{1'b0}},lzcnt};
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign srxtmp1 = rxtmp1[rs+1];
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assign srxtmp1 = rxtmp1[rs+1];
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endcase
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endcase
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wire [3*PSTWID-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgmo;
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wire [3*PSTWID-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgmo;
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// Rounding
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// Rounding
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// Gaurd, Round, and Sticky
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// Guard, Round, and Sticky
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wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
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wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
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endcase
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endcase
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wire [PSTWID-1:0] abs_tmp = so ? -tmp1_rnd : tmp1_rnd;
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wire [PSTWID-1:0] abs_tmp = so ? -tmp1_rnd : tmp1_rnd;
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always @*
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always @*
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casez({zero,inf,sig_ls[PSTWID]})
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casez({zero,inf,sig_ls[PSTWID]&1'b0})
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3'b1??: o = {PSTWID{1'b0}};
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3'b1??: o = {PSTWID{1'b0}};
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3'b01?: o = {1'b1,{PSTWID-1{1'b0}}};
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3'b01?: o = {1'b1,{PSTWID-1{1'b0}}};
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3'b001: o = {PSTWID{1'b0}};
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3'b001: o = {PSTWID{1'b0}};
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default: o = {so, abs_tmp[PSTWID-1:1]};
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default: o = {so, abs_tmp[PSTWID-1:1]};
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endcase
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endcase
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