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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positCntlo.sv] - Diff between revs 36 and 42

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Rev 36 Rev 42
Line 27... Line 27...
parameter PSTWID = `PSTWID;
parameter PSTWID = `PSTWID;
input [PSTWID-2:0] i;
input [PSTWID-2:0] i;
output [$clog2(PSTWID-2):0] o;
output [$clog2(PSTWID-2):0] o;
 
 
generate begin : gClz
generate begin : gClz
  case(PSTWID)
  if (PSTWID <= 8)
  16: cntlo16 u1 (.i({i,1'b1}), .o(o));
    cntlo8 u1 (.i({i,{9-PSTWID{1'b1}}}), .o(o));
  20: cntlo24 u1 (.i({i,1'b1,4'hF}), .o(o));
  else if (PSTWID <= 16)
  32: cntlo32 u1 (.i({i,1'b1}), .o(o));
    cntlo16 u1 (.i({i,{17-PSTWID{1'b1}}}), .o(o));
  40: cntlo48 u1 (.i({i,1'b1,8'hFF}), .o(o));
  else if (PSTWID <= 24)
  52: cntlo64 u1 (.i({i,1'b1,12'hFFF}), .o(o));
    cntlo24 u1 (.i({i,{25-PSTWID{1'b1}}}), .o(o));
  64: cntlo64 u1 (.i({i,1'b1}), .o(o));
  else if (PSTWID <= 32)
  80: cntlo80 u1 (.i({i,1'b1}), .o(o));
    cntlo32 u1 (.i({i,{33-PSTWID{1'b1}}}), .o(o));
  default:  ;
  else if (PSTWID <= 48)
  endcase
    cntlo48 u1 (.i({i,{49-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 64)
 
    cntlo64 u1 (.i({i,{65-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 80)
 
    cntlo80 u1 (.i({i,{81-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 96)
 
    cntlo96 u1 (.i({i,{97-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 128)
 
    cntlo128 u1 (.i({i,{129-PSTWID{1'b1}}}), .o(o));
end
end
endgenerate
endgenerate
 
 
endmodule
endmodule

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