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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positCntlz.sv] - Diff between revs 42 and 48

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`include "positConfig.sv"
 
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
//
//
 
import posit::PSTWID;
 
 
module positCntlz(i, o);
module positCntlz(i, o);
parameter PSTWID = `PSTWID;
parameter PSTWID = `PSTWID;
input [PSTWID-2:0] i;
input [PSTWID-2:0] i;
output [$clog2(PSTWID-1)-1:0] o;
output [$clog2(PSTWID-1)-1:0] o;
 
 

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