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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positDecompose.sv] - Diff between revs 41 and 42

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Rev 41 Rev 42
Line 36... Line 36... 
output [es-1:0] exp;              // exponent
 
output [es-1:0] exp;              // exponent
 
output [PSTWID-1-es:0] sig;       // significand
 
output [PSTWID-1-es:0] sig;       // significand
 
output zer;                       // number is zero
 
output zer;                       // number is zero
 
output inf;                       // number is infinite
 
output inf;                       // number is infinite
 
 
 
 
 
wire [rs:0] lzcnt;
 
wire [rs-1:0] lzcnt;
 
wire [rs:0] locnt;
 
wire [rs-1:0] locnt;
 
 
 
 
 
 
 
 
 
assign sgn = i[PSTWID-1];
 
assign sgn = i[PSTWID-1];
 
assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
 
assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
 
assign zer = ~|i;
 
assign zer = ~|i;

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