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`include "positConfig.sv"
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "positConfig.sv"
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import posit::*;
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// Decompose a posit number.
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// Decompose a posit number.
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module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
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module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
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`include "positSize.sv"
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parameter PSTWID = `PSTWID;
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localparam rs = $clog2(PSTWID-1);
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output sgn; // sign of number
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output sgn; // sign of number
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output rgs; // sign of regime
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output rgs; // sign of regime
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output [rs:0] rgm; // regime (absolute value)
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output [rs:0] rgm; // regime (absolute value)
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output [es-1:0] exp; // exponent
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output [es-1:0] exp; // exponent
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assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
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assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
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assign zer = ~|i;
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assign zer = ~|i;
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wire [PSTWID-1:0] ii = sgn ? -i : i;
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wire [PSTWID-1:0] ii = sgn ? -i : i;
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assign rgs = ii[PSTWID-2];
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assign rgs = ii[PSTWID-2];
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positCntlz #(PSTWID) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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positCntlz #(.PSTWID(PSTWID)) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
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positCntlo #(.PSTWID(PSTWID)) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
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assign rgm = rgs ? locnt - 1 : lzcnt;
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assign rgm = rgs ? locnt - 1 : lzcnt;
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wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
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wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
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wire [PSTWID-1:0] tmp = ii << shamt;
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wire [PSTWID-1:0] tmp = ii << shamt;
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assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
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assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
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endmodule
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endmodule
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// Decompose posit number and register outputs.
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// Decompose posit number and register outputs.
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module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
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module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
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`include "positSize.sv"
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parameter PSTWID = `PSTWID;
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input clk;
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input clk;
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input ce;
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input ce;
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output reg sgn;
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output reg sgn;
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output reg rgs;
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output reg rgs;
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wire [es-1:0] iexp;
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wire [es-1:0] iexp;
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wire [PSTWID-es-1:0] isig;
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wire [PSTWID-es-1:0] isig;
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wire izer;
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wire izer;
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wire iinf;
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wire iinf;
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positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, iinf);
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positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, izer, iinf);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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sgn = isgn;
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sgn <= isgn;
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rgs = irgs;
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rgs <= irgs;
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rgm = irgm;
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rgm <= irgm;
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exp = iexp;
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exp <= iexp;
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sig = isig;
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sig <= isig;
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inf = iinf;
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inf <= iinf;
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zer <= izer;
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end
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end
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endmodule
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endmodule
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