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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positDecompose.sv] - Diff between revs 42 and 48

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`include "positConfig.sv"
 
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
//
//
`include "positConfig.sv"
import posit::*;
 
 
// Decompose a posit number.
// Decompose a posit number.
module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
`include "positSize.sv"
parameter PSTWID = `PSTWID;
localparam rs = $clog2(PSTWID-1);
 
input [PSTWID-1:0] i;
input [PSTWID-1:0] i;
output sgn;                       // sign of number
output sgn;                       // sign of number
output rgs;                       // sign of regime
output rgs;                       // sign of regime
output [rs:0] rgm;   // regime (absolute value)
output [rs:0] rgm;   // regime (absolute value)
output [es-1:0] exp;              // exponent
output [es-1:0] exp;              // exponent
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assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
assign zer = ~|i;
assign zer = ~|i;
wire [PSTWID-1:0] ii = sgn ? -i : i;
wire [PSTWID-1:0] ii = sgn ? -i : i;
assign rgs = ii[PSTWID-2];
assign rgs = ii[PSTWID-2];
 
 
positCntlz #(PSTWID) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
positCntlz #(.PSTWID(PSTWID)) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
positCntlo #(.PSTWID(PSTWID)) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
 
 
assign rgm = rgs ? locnt - 1 : lzcnt;
assign rgm = rgs ? locnt - 1 : lzcnt;
wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
wire [PSTWID-1:0] tmp = ii << shamt;
wire [PSTWID-1:0] tmp = ii << shamt;
assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
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endmodule
endmodule
 
 
// Decompose posit number and register outputs.
// Decompose posit number and register outputs.
module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
`include "positSize.sv"
parameter PSTWID = `PSTWID;
input clk;
input clk;
input ce;
input ce;
input [PSTWID-1:0] i;
input [PSTWID-1:0] i;
output reg sgn;
output reg sgn;
output reg rgs;
output reg rgs;
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wire [es-1:0] iexp;
wire [es-1:0] iexp;
wire [PSTWID-es-1:0] isig;
wire [PSTWID-es-1:0] isig;
wire izer;
wire izer;
wire iinf;
wire iinf;
 
 
positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, iinf);
positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, izer, iinf);
 
 
always @(posedge clk)
always @(posedge clk)
if (ce) begin
if (ce) begin
  sgn = isgn;
  sgn <= isgn;
  rgs = irgs;
  rgs <= irgs;
  rgm = irgm;
  rgm <= irgm;
  exp = iexp;
  exp <= iexp;
  sig = isig;
  sig <= isig;
  inf = iinf;
  inf <= iinf;
 
  zer <= izer;
end
end
 
 
endmodule
endmodule
 
 

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