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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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import posit::*;
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module positDivide(clk, ce, a, b, o, start, done, zero, inf);
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module positDivide(clk, ce, a, b, o, start, done, zero, inf);
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1)-1;
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localparam rs = $clog2(PSTWID-1)-1;
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input clk;
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input clk;
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input ce;
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input ce;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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input [PSTWID-1:0] b;
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output reg [PSTWID-1:0] o;
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output reg [PSTWID-1:0] o;
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input start;
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input start;
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output done;
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output reg done;
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output zero;
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output reg zero;
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output inf;
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output reg inf;
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localparam N = PSTWID;
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localparam N = PSTWID;
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localparam M = N-es;
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localparam M = N-es;
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localparam Bs = $clog2(N-1);
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localparam Bs = $clog2(N-1);
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localparam NR_Iter = M > 88 ? 4 : M > 44 ? 3 : M > 22 ? 2 : M > 11 ? 1 : 0; // 2 for 32 bits, 1 for 16 bits, 0 for 8bits
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localparam NR_Iter = M > 88 ? 4 : M > 44 ? 3 : M > 22 ? 2 : M > 11 ? 1 : 0; // 2 for 32 bits, 1 for 16 bits, 0 for 8bits
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wire rgsa, rgsb;
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wire rgsa, rgsb;
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wire [es-1:0] expa, expb;
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wire [es-1:0] expa, expb;
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wire [M-1:0] siga, sigb;
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wire [M-1:0] siga, sigb;
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wire zera, zerb;
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wire zera, zerb;
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wire infa, infb;
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wire infa, infb;
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wire inf = infa|zerb;
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wire zero = zera|infb;
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positDecompose #(PSTWID,es) u1 (
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positDecompose #(PSTWID) u1 (
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.i(a),
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.i(a),
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.sgn(sa),
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.sgn(sa),
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.rgs(rgsa),
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.rgs(rgsa),
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.rgm(rgma),
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.rgm(rgma),
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.exp(expa),
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.exp(expa),
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.sig(siga),
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.sig(siga),
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.zer(zera),
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.zer(zera),
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.inf(infa)
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.inf(infa)
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);
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);
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positDecompose #(PSTWID,es) u2 (
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positDecompose #(PSTWID) u2 (
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.i(b),
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.i(b),
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.sgn(sb),
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.sgn(sb),
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.rgs(rgsb),
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.rgs(rgsb),
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.rgm(rgmb),
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.rgm(rgmb),
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.exp(expb),
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.exp(expb),
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wire [Bs+1:0] argma = rgsa ? {2'b0,rgma} : -rgma;
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wire [Bs+1:0] argma = rgsa ? {2'b0,rgma} : -rgma;
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wire [Bs+1:0] argmb = rgsb ? {2'b0,rgmb} : -rgmb;
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wire [Bs+1:0] argmb = rgsb ? {2'b0,rgmb} : -rgmb;
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generate begin : gDivLut
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generate begin : gDivLut
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if (M < AW_MAX)
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if (M < AW_MAX)
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div_lut lut1 (.clk(clk), .i({m2[M-1:0],{AW_MAX-M{1'b0}}}), .o(m2_inv0_tmp));
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div_lut lut1 (.clk(clk), .ce(ce), .i({m2[M-1:0],{AW_MAX-M{1'b0}}}), .o(m2_inv0_tmp));
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else if (M==AW_MAX)
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else if (M==AW_MAX)
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div_lut lut1 (.clk(clk), .i(m2[M-1:0]), .o(m2_inv0_tmp));
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div_lut lut1 (.clk(clk), .ce(ce), .i(m2[M-1:0]), .o(m2_inv0_tmp));
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else if (M > AW_MAX)
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else if (M > AW_MAX)
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div_lut lut1 (.clk(clk), .i(m2[M-1:M-AW_MAX]), .o(m2_inv0_tmp));
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div_lut lut1 (.clk(clk), .ce(ce), .i(m2[M-1:M-AW_MAX]), .o(m2_inv0_tmp));
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end
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end
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endgenerate
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endgenerate
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wire [IW:0] m2_inv0;
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wire [IW:0] m2_inv0;
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assign m2_inv0 = m2_inv0_tmp[15:5];
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assign m2_inv0 = m2_inv0_tmp[15:5];
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assign m2_inv[0] = {1'b0,m2_inv0,{M-IW{1'b0}},{M{1'b0}}};
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assign m2_inv[0] = {1'b0,m2_inv0,{M-IW{1'b0}},{M{1'b0}}};
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wire [2*M+1:0] m2_inv_X_m2 [NR_Iter-1:0];
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wire [2*M+1:0] m2_inv_X_m2 [NR_Iter-1:0];
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wire [M+1:0] two_m2_inv_X_m2 [NR_Iter-1:0];
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wire [M+1:0] two_m2_inv_X_m2 [NR_Iter-1:0];
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for (i = 0; i < NR_Iter; i=i+1)begin : NR_Iteration
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for (i = 0; i < NR_Iter; i=i+1)begin : NR_Iteration
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assign m2_inv_X_m2[i] = {m2_inv[i][2*M:2*M-IW*(i+1)],{2*M-IW*(i+1)-M{1'b0}}} * m2;
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assign m2_inv_X_m2[i] = {m2_inv[i][2*M:2*M-IW*(i+1)],{2*M-IW*(i+1)-M{1'b0}}} * m2;
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sub_N #(.N(M+1)) uut_sub_m2 ({1'b1,{M{1'b0}}}, {1'b0,m2_inv_X_m2[i][2*M+1:M+3],|m2_inv_X_m2[i][M+2:0]}, two_m2_inv_X_m2[i]);
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assign two_m2_inv_X_m2[i] = {1'b1,{M{1'b0}}} - {1'b0,m2_inv_X_m2[i][2*M+1:M+3],|m2_inv_X_m2[i][M+2:0]};
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assign m2_inv[i+1] = {m2_inv[i][2*M:2*M-IW*(i+1)],{M-IW*(i+1){1'b0}}} * {two_m2_inv_X_m2[i][M-1:0],1'b0};
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assign m2_inv[i+1] = {m2_inv[i][2*M:2*M-IW*(i+1)],{M-IW*(i+1){1'b0}}} * {two_m2_inv_X_m2[i][M-1:0],1'b0};
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end
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end
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end
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end
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else begin
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else begin
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assign m2_inv[0] = {1'b0,m2_inv0,{M{1'b0}}};
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assign m2_inv[0] = {1'b0,m2_inv0,{M{1'b0}}};
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end
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end
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assign div_m = ~|sigb[M-2:0] ? {1'b0,m1,{M{1'b0}}} : m1 * m2_inv[NR_Iter][2*M:M];
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assign div_m4 = ~|sigb[M-2:0] ? {1'b0,m1,{M{1'b0}}} : m1 * m2_inv[NR_Iter][2*M:M];
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end
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end
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endgenerate
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endgenerate
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// Put in some pipeline registers to allow tools to retime the NR iterations.
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delay #(.WID(PSTWID), .DEP(4)) ud4 (.clk(clk), .ce(ce), .i(div_m4), .o(div_m));
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delay4 #(M*2+2) ud1 (.clk(clk), .ce(ce), .i(div_m), .o(div_m4));
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delay #(.WID(1),.DEP(5)) ud1 (.clk(clk), .ce(ce), .i(start), .o(done));
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wire d1;
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delay #(.WID(1),.DEP(5)) ud2 (.clk(clk), .ce(ce), .i(infa|infb), .o(inf));
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delay4 #(1) ud2 (.clk(clk), .ce(ce), .i(start), .o(d1));
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delay #(.WID(1),.DEP(5)) ud3 (.clk(clk), .ce(ce), .i(zera|zerb), .o(zero));
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delay4 #(1) ud3 (.clk(clk), .ce(ce), .i(d1), .o(done));
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wire div_m_udf = div_m4[2*M+1];
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wire div_m_udf = div_m[2*M+1];
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wire [2*M+1:0] div_mN = ~div_m_udf ? div_m4 << 1'b1 : div_m4;
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wire [2*M+1:0] div_mN = ~div_m_udf ? div_m << 1'b1 : div_m;
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//Exponent and Regime Computation
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//Exponent and Regime Computation
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wire bin = (~|sigb[M-2:0] | div_m_udf) ? 0 : 1;
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wire bin = (~|sigb[M-2:0] | div_m_udf) ? 0 : 1;
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wire [Bs+es+1:0] div_e = {argma, expa} - {argmb, expb} - bin;// 1 + ~|mant2 + div_m_udf;
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wire [Bs+es+1:0] div_e = {argma, expa} - {argmb, expb} - bin;// 1 + ~|mant2 + div_m_udf;
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wire [es-1:0] e_o = div_e[es-1:0];
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wire [es-1:0] e_o = div_e[es-1:0];
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wire [N:0] tmp1_o_rnd_ulp = tmp1_o[2*N-1+3:N+3] + rnd_ulp;
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wire [N:0] tmp1_o_rnd_ulp = tmp1_o[2*N-1+3:N+3] + rnd_ulp;
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wire [N-1:0] tmp1_o_rnd = (r_o < M-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];
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wire [N-1:0] tmp1_o_rnd = (r_o < M-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];
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//Final Output
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//Final Output
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wire [N-1:0] tmp1_oN = so ? -tmp1_o_rnd : tmp1_o_rnd;
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wire [N-1:0] tmp1_oN = so ? -tmp1_o_rnd : tmp1_o_rnd;
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assign o = inf|zero|(~div_mN[2*M+1]) ? {inf,{N-1{1'b0}}} : {so, tmp1_oN[N-1:1]};
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always @(posedge clk)
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if (ce) o <= inf|zero|(~div_mN[2*M+1]) ? {inf,{N-1{1'b0}}} : {so, tmp1_oN[N-1:1]};
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endmodule
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endmodule
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