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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positDivide.sv] - Diff between revs 43 and 48

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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
 
 
`include "positConfig.sv"
import posit::*;
 
 
module positDivide(clk, ce, a, b, o, start, done, zero, inf);
module positDivide(clk, ce, a, b, o, start, done, zero, inf);
`include "positSize.sv"
 
localparam rs = $clog2(PSTWID-1)-1;
localparam rs = $clog2(PSTWID-1)-1;
input clk;
input clk;
input ce;
input ce;
input [PSTWID-1:0] a;
input [PSTWID-1:0] a;
input [PSTWID-1:0] b;
input [PSTWID-1:0] b;
output reg [PSTWID-1:0] o;
output reg [PSTWID-1:0] o;
input start;
input start;
output done;
output reg done;
output zero;
output reg zero;
output inf;
output reg inf;
 
 
localparam N = PSTWID;
localparam N = PSTWID;
localparam M = N-es;
localparam M = N-es;
localparam Bs = $clog2(N-1);
localparam Bs = $clog2(N-1);
localparam NR_Iter = M > 88 ? 4 : M > 44 ? 3 : M > 22 ? 2 : M > 11 ? 1 : 0;             // 2 for 32 bits, 1 for 16 bits, 0 for 8bits
localparam NR_Iter = M > 88 ? 4 : M > 44 ? 3 : M > 22 ? 2 : M > 11 ? 1 : 0;             // 2 for 32 bits, 1 for 16 bits, 0 for 8bits
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wire rgsa, rgsb;
wire rgsa, rgsb;
wire [es-1:0] expa, expb;
wire [es-1:0] expa, expb;
wire [M-1:0] siga, sigb;
wire [M-1:0] siga, sigb;
wire zera, zerb;
wire zera, zerb;
wire infa, infb;
wire infa, infb;
wire inf = infa|zerb;
 
wire zero = zera|infb;
 
 
 
positDecompose #(PSTWID,es) u1 (
positDecompose #(PSTWID) u1 (
  .i(a),
  .i(a),
  .sgn(sa),
  .sgn(sa),
  .rgs(rgsa),
  .rgs(rgsa),
  .rgm(rgma),
  .rgm(rgma),
  .exp(expa),
  .exp(expa),
  .sig(siga),
  .sig(siga),
  .zer(zera),
  .zer(zera),
  .inf(infa)
  .inf(infa)
);
);
 
 
positDecompose #(PSTWID,es) u2 (
positDecompose #(PSTWID) u2 (
  .i(b),
  .i(b),
  .sgn(sb),
  .sgn(sb),
  .rgs(rgsb),
  .rgs(rgsb),
  .rgm(rgmb),
  .rgm(rgmb),
  .exp(expb),
  .exp(expb),
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wire [Bs+1:0] argma = rgsa ? {2'b0,rgma} : -rgma;
wire [Bs+1:0] argma = rgsa ? {2'b0,rgma} : -rgma;
wire [Bs+1:0] argmb = rgsb ? {2'b0,rgmb} : -rgmb;
wire [Bs+1:0] argmb = rgsb ? {2'b0,rgmb} : -rgmb;
 
 
generate begin : gDivLut
generate begin : gDivLut
if (M < AW_MAX)
if (M < AW_MAX)
div_lut lut1 (.clk(clk), .i({m2[M-1:0],{AW_MAX-M{1'b0}}}), .o(m2_inv0_tmp));
div_lut lut1 (.clk(clk), .ce(ce), .i({m2[M-1:0],{AW_MAX-M{1'b0}}}), .o(m2_inv0_tmp));
else if (M==AW_MAX)
else if (M==AW_MAX)
div_lut lut1 (.clk(clk), .i(m2[M-1:0]), .o(m2_inv0_tmp));
div_lut lut1 (.clk(clk), .ce(ce), .i(m2[M-1:0]), .o(m2_inv0_tmp));
else if (M > AW_MAX)
else if (M > AW_MAX)
div_lut lut1 (.clk(clk), .i(m2[M-1:M-AW_MAX]), .o(m2_inv0_tmp));
div_lut lut1 (.clk(clk), .ce(ce), .i(m2[M-1:M-AW_MAX]), .o(m2_inv0_tmp));
end
end
endgenerate
endgenerate
 
 
wire [IW:0] m2_inv0;
wire [IW:0] m2_inv0;
assign m2_inv0 = m2_inv0_tmp[15:5];
assign m2_inv0 = m2_inv0_tmp[15:5];
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                assign m2_inv[0] = {1'b0,m2_inv0,{M-IW{1'b0}},{M{1'b0}}};
                assign m2_inv[0] = {1'b0,m2_inv0,{M-IW{1'b0}},{M{1'b0}}};
                wire [2*M+1:0] m2_inv_X_m2 [NR_Iter-1:0];
                wire [2*M+1:0] m2_inv_X_m2 [NR_Iter-1:0];
                wire [M+1:0] two_m2_inv_X_m2 [NR_Iter-1:0];
                wire [M+1:0] two_m2_inv_X_m2 [NR_Iter-1:0];
                for (i = 0; i < NR_Iter; i=i+1)begin : NR_Iteration
                for (i = 0; i < NR_Iter; i=i+1)begin : NR_Iteration
                        assign m2_inv_X_m2[i] = {m2_inv[i][2*M:2*M-IW*(i+1)],{2*M-IW*(i+1)-M{1'b0}}} * m2;
                        assign m2_inv_X_m2[i] = {m2_inv[i][2*M:2*M-IW*(i+1)],{2*M-IW*(i+1)-M{1'b0}}} * m2;
                        sub_N #(.N(M+1)) uut_sub_m2 ({1'b1,{M{1'b0}}}, {1'b0,m2_inv_X_m2[i][2*M+1:M+3],|m2_inv_X_m2[i][M+2:0]}, two_m2_inv_X_m2[i]);
                        assign two_m2_inv_X_m2[i] = {1'b1,{M{1'b0}}} - {1'b0,m2_inv_X_m2[i][2*M+1:M+3],|m2_inv_X_m2[i][M+2:0]};
                        assign m2_inv[i+1] = {m2_inv[i][2*M:2*M-IW*(i+1)],{M-IW*(i+1){1'b0}}} * {two_m2_inv_X_m2[i][M-1:0],1'b0};
                        assign m2_inv[i+1] = {m2_inv[i][2*M:2*M-IW*(i+1)],{M-IW*(i+1){1'b0}}} * {two_m2_inv_X_m2[i][M-1:0],1'b0};
                end
                end
        end
        end
        else begin
        else begin
                assign m2_inv[0] = {1'b0,m2_inv0,{M{1'b0}}};
                assign m2_inv[0] = {1'b0,m2_inv0,{M{1'b0}}};
        end
        end
        assign div_m = ~|sigb[M-2:0] ? {1'b0,m1,{M{1'b0}}} : m1 * m2_inv[NR_Iter][2*M:M];
        assign div_m4 = ~|sigb[M-2:0] ? {1'b0,m1,{M{1'b0}}} : m1 * m2_inv[NR_Iter][2*M:M];
end
end
endgenerate
endgenerate
 
 
// Put in some pipeline registers to allow tools to retime the NR iterations.
delay #(.WID(PSTWID), .DEP(4)) ud4 (.clk(clk), .ce(ce), .i(div_m4), .o(div_m));
delay4 #(M*2+2) ud1 (.clk(clk), .ce(ce), .i(div_m), .o(div_m4));
delay #(.WID(1),.DEP(5)) ud1 (.clk(clk), .ce(ce), .i(start), .o(done));
wire d1;
delay #(.WID(1),.DEP(5)) ud2 (.clk(clk), .ce(ce), .i(infa|infb), .o(inf));
delay4 #(1) ud2 (.clk(clk), .ce(ce), .i(start), .o(d1));
delay #(.WID(1),.DEP(5)) ud3 (.clk(clk), .ce(ce), .i(zera|zerb), .o(zero));
delay4 #(1) ud3 (.clk(clk), .ce(ce), .i(d1), .o(done));
 
 
 
wire div_m_udf = div_m4[2*M+1];
wire div_m_udf = div_m[2*M+1];
wire [2*M+1:0] div_mN = ~div_m_udf ? div_m4 << 1'b1 : div_m4;
wire [2*M+1:0] div_mN = ~div_m_udf ? div_m << 1'b1 : div_m;
 
 
//Exponent and Regime Computation
//Exponent and Regime Computation
wire bin = (~|sigb[M-2:0] | div_m_udf) ? 0 : 1;
wire bin = (~|sigb[M-2:0] | div_m_udf) ? 0 : 1;
wire [Bs+es+1:0] div_e = {argma, expa} - {argmb, expb} - bin;// 1 + ~|mant2 + div_m_udf;
wire [Bs+es+1:0] div_e = {argma, expa} - {argmb, expb} - bin;// 1 + ~|mant2 + div_m_udf;
wire [es-1:0] e_o = div_e[es-1:0];
wire [es-1:0] e_o = div_e[es-1:0];
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wire [N:0] tmp1_o_rnd_ulp = tmp1_o[2*N-1+3:N+3] + rnd_ulp;
wire [N:0] tmp1_o_rnd_ulp = tmp1_o[2*N-1+3:N+3] + rnd_ulp;
wire [N-1:0] tmp1_o_rnd = (r_o < M-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];
wire [N-1:0] tmp1_o_rnd = (r_o < M-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];
 
 
//Final Output
//Final Output
wire [N-1:0] tmp1_oN = so ? -tmp1_o_rnd : tmp1_o_rnd;
wire [N-1:0] tmp1_oN = so ? -tmp1_o_rnd : tmp1_o_rnd;
assign o = inf|zero|(~div_mN[2*M+1]) ? {inf,{N-1{1'b0}}} : {so, tmp1_oN[N-1:1]};
always @(posedge clk)
 
  if (ce) o <= inf|zero|(~div_mN[2*M+1]) ? {inf,{N-1{1'b0}}} : {so, tmp1_oN[N-1:1]};
 
 
endmodule
endmodule

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