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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positFDP.sv] - Diff between revs 42 and 48

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Rev 42 Rev 48
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
 
 
`include "positConfig.sv"
import posit::*;
 
 
module positFDP(op, a, b, c, d, o, zero, inf);
module positFDP(op, a, b, c, d, o, zero, inf);
`include "positSize.sv"
 
input op;
input op;
input [PSTWID-1:0] a;
input [PSTWID-1:0] a;
input [PSTWID-1:0] b;
input [PSTWID-1:0] b;
input [PSTWID-1:0] c;
input [PSTWID-1:0] c;
input [PSTWID-1:0] d;
input [PSTWID-1:0] d;
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output inf;
output inf;
 
 
wire [PSTWID+es+(PSTWID-es)*2-1:0] o1;
wire [PSTWID+es+(PSTWID-es)*2-1:0] o1;
wire [PSTWID+es+(PSTWID-es)*2-1:0] o2;
wire [PSTWID+es+(PSTWID-es)*2-1:0] o2;
 
 
positFDPMul #(.PSTWID(PSTWID), .es(es)) u1 (a, b, o1, zero1, inf1);
positFDPMul u1 (a, b, o1, zero1, inf1);
positFDPMul #(.PSTWID(PSTWID), .es(es)) u2 (c, d, o2, zero2, inf2);
positFDPMul u2 (c, d, o2, zero2, inf2);
positFDPAddsub #(.PSTWID(PSTWID), .es(es)) u3 (op, o1, o2, o, zero, inf);
positFDPAddsub u3 (op, o1, o2, o, zero, inf);
 
 
endmodule
endmodule

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