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`include "positConfig.sv"
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`include "positConfig.sv"
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module positMul(a, b, o, zero, inf);
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module positMul(a, b, o, zero, inf);
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`include "positSize.sv"
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1)-1;
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localparam rs = $clog2(PSTWID-1);
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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input [PSTWID-1:0] b;
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output reg [PSTWID-1:0] o;
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output reg [PSTWID-1:0] o;
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output zero;
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output zero;
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output inf;
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output inf;
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wire [es-1:0] exp = rxtmp[es-1:0];
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wire [es-1:0] exp = rxtmp[es-1:0];
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// Take absolute value of regime portion
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// Take absolute value of regime portion
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wire srxtmp = rxtmp[rs+es+1];
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wire srxtmp = rxtmp[rs+es+1];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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// Compute the length of the regime bit string, +1 for positive regime
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// Compute the length of the regime bit string, +1 for positive regime
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wire [rs:0] rgml = srxtmp ? rxtmp2c[rs+es:es] : rxtmp2c[rs+es:es] + 2'd1;
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wire [rs+es+1:0] rxn = rxtmp[rs+es+1] ? rxtmp2c : rxtmp;
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//assign r_o = (~exp_o[es+Bs+1] || |(exp_oN[es-1:0])) ? exp_oN[es+Bs:es] + 1 : exp_oN[es+Bs:es];
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wire [rs:0] rgml = (~srxtmp | |(rxn[es-1:0])) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
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// Build expanded posit number:
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// Build expanded posit number:
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// trim one leading bit off the product bits
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// trim one leading bit off the product bits
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// and keep guard, round bits, and create sticky bit
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// and keep guard, round bits, and create sticky bit
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wire [PSTWID*2-1+3:0] tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,prod1[(PSTWID-es)*2-2:(PSTWID-es-2)],|prod1[(PSTWID-es-3):0]};
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wire [PSTWID*2-1+3:0] tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,prod1[(PSTWID-es)*2-2:(PSTWID-es-2)],|prod1[(PSTWID-es-3):0]};
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wire [PSTWID*3-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgml;
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wire [PSTWID*3-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgml;
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// Rounding
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// Rounding
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// Gaurd, Round, and Sticky
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// Guard, Round, and Sticky
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wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
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wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
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