URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positMul.sv] - Diff between revs 41 and 48

Rev 41	Rev 48
Line 23...	Line 23...
`// You should have received a copy of the GNU General Public License`	`// You should have received a copy of the GNU General Public License`
`// along with this program. If not, see .`	`// along with this program. If not, see .`
`//`	`//`
`// ============================================================================`	`// ============================================================================`

`include "positConfig.sv"	`import posit::*;`

`module positMul(a, b, o, zero, inf);`	`module positMul(a, b, o, zero, inf);`
`include "positSize.sv"
`localparam rs = $clog2(PSTWID-1);`
`input [PSTWID-1:0] a;`	`input [PSTWID-1:0] a;`
`input [PSTWID-1:0] b;`	`input [PSTWID-1:0] b;`
`output reg [PSTWID-1:0] o;`	`output reg [PSTWID-1:0] o;`
`output zero;`	`output zero;`
`output inf;`	`output inf;`
Line 47...	Line 45...
`wire infa, infb;`	`wire infa, infb;`
`wire [PSTWID-1:0] aa, bb;`	`wire [PSTWID-1:0] aa, bb;`
`wire inf = infa\|infb;`	`wire inf = infa\|infb;`
`wire zero = zera\|zerb;`	`wire zero = zera\|zerb;`

`positDecompose #(PSTWID,es) u1 (`	`positDecompose #(PSTWID) u1 (`
`.i(a),`	`.i(a),`
`.sgn(sa),`	`.sgn(sa),`
`.rgs(rgsa),`	`.rgs(rgsa),`
`.rgm(rgma),`	`.rgm(rgma),`
`.exp(expa),`	`.exp(expa),`
`.sig(siga),`	`.sig(siga),`
`.zer(zera),`	`.zer(zera),`
`.inf(infa)`	`.inf(infa)`
`);`	`);`

`positDecompose #(PSTWID,es) u2 (`	`positDecompose #(PSTWID) u2 (`
`.i(b),`	`.i(b),`
`.sgn(sb),`	`.sgn(sb),`
`.rgs(rgsb),`	`.rgs(rgsb),`
`.rgm(rgmb),`	`.rgm(rgmb),`
`.exp(expb),`	`.exp(expb),`