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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positMultiply.sv] - Diff between revs 47 and 48

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Rev 47 Rev 48
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      positMultiply.v
//      positMultiply.sv
//    - posit number multiplier, pipelined with latency of 13
//    - posit number multiplier, pipelined with latency of 13
//    - can issue every other clock cycle
//    - can issue every other clock cycle
//    - parameterized width
//    - parameterized width
//
//
//
//
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
 
 
`include "positConfig.sv"
import posit::*;
 
 
module positMultiply(clk, ce, a, b, o, zero, inf);
module positMultiply(clk, ce, a, b, o, zero, inf);
`include "positSize.sv"
 
localparam rs = $clog2(PSTWID-1);
 
input clk;
input clk;
input ce;
input ce;
input [PSTWID-1:0] a;
input [PSTWID-1:0] a;
input [PSTWID-1:0] b;
input [PSTWID-1:0] b;
output reg [PSTWID-1:0] o;
output reg [PSTWID-1:0] o;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #1
// Clock #1
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 
positDecomposeReg #(PSTWID,es) u1 (
positDecomposeReg #(PSTWID) u1 (
  .clk(clk),
  .clk(clk),
  .ce(ce),
  .ce(ce),
  .i(a),
  .i(a),
  .sgn(sa),
  .sgn(sa),
  .rgs(rgsa),
  .rgs(rgsa),
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  .sig(siga),
  .sig(siga),
  .zer(zera),
  .zer(zera),
  .inf(infa)
  .inf(infa)
);
);
 
 
positDecomposeReg #(PSTWID,es) u2 (
positDecomposeReg #(PSTWID) u2 (
  .clk(clk),
  .clk(clk),
  .ce(ce),
  .ce(ce),
  .i(b),
  .i(b),
  .sgn(sb),
  .sgn(sb),
  .rgs(rgsb),
  .rgs(rgsb),

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