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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positSqrt.sv] - Diff between revs 39 and 41

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Rev 39 Rev 41
Line 7... Line 7...
//
//
//      positSqrt.v
//      positSqrt.v
//    - posit number square root function
//    - posit number square root function
//    - parameterized width
//    - parameterized width
//
//
/////////////////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////////////////
 
// This function currently only seems to work with even sizes of
 
// exponents.
 
/////////////////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////////////////
 
//
 
//
//
// This source file is free software: you can redistribute it and/or modify
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// (at your option) any later version.
Line 66... Line 59...
  .zer(zeri),
  .zer(zeri),
  .inf(infi)
  .inf(infi)
);
);
 
 
assign so = si;                         // square root of positive numbers only
assign so = si;                         // square root of positive numbers only
 
// Compute length of significand. This length is needed to align the
 
// significand input to the square root module.
 
//wire [rs+1:0] rgml1 = rgsi ? rgmi + 2'd2 : rgmi + 2'd1;
 
//wire [rs+1:0] sigl = PSTWID-rgml1-es-1;
 
// The length could be zero or less
 
//wire [rs:0] sigl1 = sigl[rs+1] ? {rs{1'b0}} : sigl;
 
 
 
// Compute exponent
wire [rs+1:0] rgm1 = rgsi ? rgmi : -rgmi;
wire [rs+1:0] rgm1 = rgsi ? rgmi : -rgmi;
wire [rs+es+1:0] rx1 = {rgm1,expi};
wire [rs+es+1:0] rx1 = {rgm1,expi};
// If exponent is odd, make it even. May need to shift the significand later.
// If exponent is odd, make it even. May need to shift the significand later.
wire [rs+es+1:0] rxtmp = {{2{rx1[rs+es+1]}},rx1} >> 1;   // right shift takes square root of exponent
wire [rs+es+1:0] rxtmp = {{2{rx1[rs+es+1]}},rx1} >> 1;   // right shift takes square root of exponent
 
 
assign sqrinf = infi;
assign sqrinf = infi;
assign sqrneg = so;
assign sqrneg = so;
// If the exponent was made even, shift the significand left.
// If the exponent was made even, shift the significand left.
wire [PSTWID-1:0] sig1 = rx1[0] ? {sigi,1'b0} : {1'b0,sigi};
wire [PSTWID-1:0] sig1 = (rx1[0] ^ ~es[0]) ? {sigi,1'b0} : {1'b0,sigi};
 
 
wire ldd;
wire ldd;
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(start), .o(ldd));
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(start), .o(ldd));
wire [PSTWID*3-1:0] sqrto;
wire [PSTWID*3-1:0] sqrto;
 
 
Line 89... Line 90...
(
(
        .rst(rst),
        .rst(rst),
        .clk(clk),
        .clk(clk),
        .ce(ce),
        .ce(ce),
        .ld(ldd),
        .ld(ldd),
        .a({sig1,{(PSTWID/2+1-(PSTWID%2)){1'b0}}}),
        // Align the input according to odd/even length
 
        .a({sig1,{PSTWID/2{1'b0}}}),
        .o(sqrto),
        .o(sqrto),
        .done(done),
        .done(done),
        .lzcnt(lzcnt)
        .lzcnt(lzcnt)
);
);
 
 

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