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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positToFp.sv] - Diff between revs 36 and 48

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Rev 36 Rev 48
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      positToFp.v
//      positToFp.sv
//    - posit number to floating point convertor
//    - posit number to floating point convertor
//    - can issue every clock cycle
//    - can issue every clock cycle
//    - parameterized width
//    - parameterized width
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
 
 
`include "positConfig.sv"
import posit::*;
`include "fpConfig.sv"
import fp::*;
`include "fpTypes.sv"
`include "../fpu/fpTypes.sv"
 
 
module positToFp(i, o);
module positToFp(i, o);
parameter FPWID = 32;
 
`include "fpSize.sv"
 
`include "positSize.sv"
 
input [FPWID-1:0] i;
input [FPWID-1:0] i;
output reg [FPWID-1:0] o;
output reg [FPWID-1:0] o;
 
 
parameter BIAS = {1'b0,{EMSB{1'b1}}};
parameter BIAS = {1'b0,{EMSB{1'b1}}};
localparam N = FPWID;
localparam N = FPWID;
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wire [es-1:0] exp;
wire [es-1:0] exp;
wire [N-es-1:0] sig;
wire [N-es-1:0] sig;
wire zer;
wire zer;
wire inf;
wire inf;
 
 
positDecompose #(.PSTWID(PSTWID), .es(es)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf));
positDecompose #(.PSTWID(PSTWID)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf));
 
 
wire [N-1:0] m = {sig,{es{1'b0}}};
wire [N-1:0] m = {sig,{es{1'b0}}};
wire [EO+1:0] e;
wire [EO+1:0] e;
assign e = {(rgs ? {{EO-es-Bs+1{1'b0}},rgm} : -{{EO-es-Bs+1{1'b0}},rgm}),exp} + BIAS;
assign e = {(rgs ? {{EO-es-Bs+1{1'b0}},rgm} : -{{EO-es-Bs+1{1'b0}},rgm}),exp} + BIAS;
wire exv = |e[EO:E];
wire exv = |e[EO:E];

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