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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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import posit::*;
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module positToInt(i, o);
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module positToInt(clk, ce, i, o);
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`include "positSize.sv"
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input clk;
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input ce;
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output reg [PSTWID-1:0] o;
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output reg [PSTWID-1:0] o;
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localparam N = PSTWID;
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localparam N = PSTWID;
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localparam Bs = $clog2(PSTWID-1);
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localparam Bs = $clog2(PSTWID-1);
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wire [es-1:0] exp;
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wire [es-1:0] exp;
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wire [N-es-1:0] sig;
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wire [N-es-1:0] sig;
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wire zer;
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wire zer;
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wire inf;
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wire inf;
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positDecompose #(.PSTWID(PSTWID), .es(es)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf));
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #1
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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positDecomposeReg #(.PSTWID(PSTWID)) u1 (
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.clk(clk),
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.ce(ce),
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.i(i),
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.sgn(sgn),
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.rgs(rgs),
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.rgm(rgm),
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.exp(exp),
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.sig(sig),
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.zer(zer),
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.inf(inf)
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);
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wire [N-1:0] m = {sig,{es{1'b0}}};
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wire [N-1:0] m = {sig,{es{1'b0}}};
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wire isZero = zer;
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wire isZero = zer;
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wire [15:0] argm = rgs ? rgm : -rgm;
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wire [15:0] ex1 = (argm << es) + exp;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire exv = ~ex1[15] && ex1 > PSTWID-1;
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// Clock #2
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wire [N*2-1:0] mo = {m,{N{1'b0}}} >> (PSTWID-ex1-1);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire L = mo[N];
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reg [15:0] argm2;
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wire G = mo[N-1];
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reg [es-1:0] exp2;
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wire R = mo[N-2];
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reg [N-1:0] m2;
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wire St = |mo[N-3:0];
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always @(posedge clk)
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if (ce) exp2 <= exp;
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always @(posedge clk)
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if (ce) m2 <= m;
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always @(posedge clk)
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if (ce) argm2 <= rgs ? rgm : -rgm;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #3
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [15:0] ex3;
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reg [N-1:0] m3;
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always @(posedge clk)
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if (ce) ex3 <= (argm2 << es) + exp2;
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always @(posedge clk)
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if (ce) m3 <= m2;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #4
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg exv4;
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reg [15:0] ex4;
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reg [N*2-1:0] mo4;
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always @(posedge clk)
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if (ce) exv4 <= ~ex3[15] && ex3 > PSTWID-1;
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always @(posedge clk)
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if (ce) ex4 <= ex3;
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always @(posedge clk)
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if (ce) mo4 = {m3,{N{1'b0}}} >> (PSTWID-ex3-1);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #5
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [15:0] ex5;
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reg [N*2-1:0] mo5;
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reg L, G, R, St;
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always @(posedge clk)
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if (ce) ex5 <= ex4;
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always @(posedge clk)
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if (ce) mo5 = mo4;
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always @(posedge clk)
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if (ce) L <= mo4[N];
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always @(posedge clk)
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if (ce) G <= mo4[N-1];
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always @(posedge clk)
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if (ce) R <= mo4[N-2];
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always @(posedge clk)
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if (ce) St <= |mo4[N-3:0];
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #6
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// If regime+exp == -1 then the value is 0.5 or greater, so round up.
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// If regime+exp == -1 then the value is 0.5 or greater, so round up.
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// If the regime+exp < -1 then the values is 0.25 or less, do not round up.
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// If the regime+exp < -1 then the values is 0.25 or less, do not round up.
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// Otherwise use rounding rules.
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// Otherwise use rounding rules.
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wire ulp = (~ex1[15] && ((G & (R | St)) | (L & G & ~(R | St)))) ||
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reg [N*2-1:0] mo6;
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(ex1==16'hFFFF);
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reg ulp;
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always @(posedge clk)
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if (ce) mo6 = mo5;
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always @(posedge clk)
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if (ce) ulp <= (~ex5[15] && ((G & (R | St)) | (L & G & ~(R | St)))) ||
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(ex5==16'hFFFF);
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID-1:0] tmp = ~rgs ? rnd_ulp : mo[N*2-1:N] + rnd_ulp;
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always @*
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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casez({isZero,inf|exv}) // exponent all ones or exponent overflow?
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// Clock #7
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [PSTWID-1:0] tmp7;
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wire rgs6;
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delay #(.WID(1), .DEP(5)) ud1 (.clk(clk), .ce(ce), .i(rgs), .o(rgs6));
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always @(posedge clk)
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if (ce) tmp7 <= ~rgs6 ? rnd_ulp : mo6[N*2-1:N] + rnd_ulp;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #8
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire isZero7, inf7, sgn7, exv7;
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delay #(.WID(1), .DEP(6)) ud2 (.clk(clk), .ce(ce), .i(isZero), .o(isZero7));
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delay #(.WID(1), .DEP(6)) ud3 (.clk(clk), .ce(ce), .i(inf), .o(inf7));
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delay #(.WID(1), .DEP(6)) ud4 (.clk(clk), .ce(ce), .i(sgn), .o(sgn7));
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delay #(.WID(1), .DEP(3)) ud5 (.clk(clk), .ce(ce), .i(exv4), .o(exv7));
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always @(posedge clk)
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if (ce)
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casez({isZero7,inf7|exv7,sgn7}) // exponent all ones or exponent overflow?
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// convert to +0.0 zero-in zero-out (the sign will always be plus)
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// convert to +0.0 zero-in zero-out (the sign will always be plus)
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2'b1?: o = {PSTWID{1'b0}};
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3'b1??: o <= {PSTWID{1'b0}};
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// Infinity in or exponent overflow in conversion = infinity out
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// Infinity in or exponent overflow in conversion = infinity out
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2'b01: o = {1'b1,{PSTWID-1{1'b0}}};
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3'b01?: o <= {1'b1,{PSTWID-1{1'b0}}};
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// Other numbers
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3'b001: o <= ~tmp7 + 2'd1;
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default: o = sgn ? -tmp : tmp;
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3'b000: o <= tmp7;
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endcase
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endcase
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endmodule
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endmodule
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