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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [DivGoldschmidt.v] - Diff between revs 14 and 26

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Rev 14 Rev 26
Line 23... Line 23...
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//                                                                          
//
//
// ============================================================================
// ============================================================================
//
//
module DivGoldschmidt(rst, clk, ld, a, b, q, f0, done, lzcnt);
module DivGoldschmidt(rst, clk, ld, a, b, q, done, lzcnt);
parameter WID=32;
parameter WID=32;
parameter WHOLE=16;
parameter WHOLE=16;
parameter POINTS=16;
parameter POINTS=16;
parameter LEFT=1'b1;
parameter LEFT=1'b1;
localparam SIZE=WID+WHOLE;
localparam SIZE=WID+WHOLE;
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input clk;
input clk;
input ld;
input ld;
input [WID-1:0] a;
input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] b;
output reg [WID*2-1:0] q;
output reg [WID*2-1:0] q;
output reg [SIZE-1:0] f0;
 
output reg done;
output reg done;
output reg [7:0] lzcnt;
output reg [7:0] lzcnt;
parameter IDLE = 2'd0;
parameter IDLE = 2'd0;
parameter DIV = 2'd1;
parameter DIV = 2'd1;
parameter DONE = 2'd2;
parameter DONE = 2'd2;
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                        if (shift_left) begin
                        if (shift_left) begin
                                if (LEFT) begin
                                if (LEFT) begin
                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
                                        f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
 
                                end
                                end
                                else begin
                                else begin
                                        N <= {16'd0,a,{WHOLE{1'b0}}};
                                        N <= {16'd0,a,{WHOLE{1'b0}}};
                                        D <= {16'd0,b,{WHOLE{1'd0}}};
                                        D <= {16'd0,b,{WHOLE{1'd0}}};
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
                                        f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
 
                                end
                                end
                        end
                        end
                        else begin
                        else begin
                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
                                f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
 
                        end
                        end
                        count <= 0;
                        count <= 0;
                        state <= DIV;
                        state <= DIV;
                end
                end
        end
        end
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reg rst;
reg rst;
reg clk;
reg clk;
reg ld;
reg ld;
wire done;
wire done;
wire [WID*2-1:0] qo;
wire [WID*2-1:0] qo;
wire [7:0] f0;
 
reg [3:0] state;
reg [3:0] state;
reg [3:0] a, b;
reg [3:0] a, b;
reg [7:0] count;
reg [7:0] count;
 
 
initial begin
initial begin
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//      .isDivi(1'b0),
//      .isDivi(1'b0),
        .a(a),
        .a(a),
        .b(b),
        .b(b),
//      .imm(64'd123),
//      .imm(64'd123),
        .q(qo),
        .q(qo),
        .f0(f0),
 
//      .ro(ro),
//      .ro(ro),
//      .dvByZr(),
//      .dvByZr(),
        .left_right(),
        .done(done),
        .shift(),
        .lzcnt()
        .done(done)
 
);
);
 
 
endmodule
endmodule
 
 
 
 
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