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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub.v
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// fpAddsub.v
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wire [FMSB+3:0] oa = xa_gt_xb1 ? {fracta1,2'b0} : md1;
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wire [FMSB+3:0] oa = xa_gt_xb1 ? {fracta1,2'b0} : md1;
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wire [FMSB+3:0] ob = xa_gt_xb1 ? md1 : {fractb1,2'b0};
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wire [FMSB+3:0] ob = xa_gt_xb1 ? md1 : {fractb1,2'b0};
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wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob;
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wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob;
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wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa;
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wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa;
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wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb;
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wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb;
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wire xoinf = &xo;
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always @*
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always @*
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casez({aInf1&bInf1,aNan1,bNan1})
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casez({aInf1&bInf1,aNan1,bNan1,xoinf})
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3'b1??: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b1???: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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3'b01?: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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4'b01??: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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3'b001: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo1 = 1'd0;
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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endcase
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endcase
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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