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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Stratford
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub.v
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// - floating point adder/subtracter
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// - two cycle latency
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// - can issue every clock cycle
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// - parameterized width
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// - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// fpAddsub.v
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// - floating point adder/subtracter
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// - two cycle latency
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// - can issue every clock cycle
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// - parameterized width
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// - IEEE 754 representation
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//
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// This adder/subtractor handles denormalized numbers.
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// It has a two cycle latency.
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// The output format is of an internal expanded representation
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// in preparation to be fed into a normalization unit, then
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// rounding. Basically, it's the same as the regular format
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// except the mantissa is doubled in size, the leading two
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// bits of which are assumed to be whole bits.
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// ============================================================================
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// ============================================================================
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//
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module fpAddsub(clk, ce, rm, op, a, b, o);
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module fpAddsub(clk, ce, rm, op, a, b, o);
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parameter WID = 32;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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localparam WX = 3;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+1)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + WX + EMSB + 1;
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input clk; // system clock
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input clk; // system clock
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input ce; // core clock enable
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input ce; // core clock enable
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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input [WID-1:0] a; // operand a
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input [WID-1:0] a; // operand a
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input [WID-1:0] b; // operand b
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input [WID-1:0] b; // operand b
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output [EX+1:0] o; // output
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output [EX:0] o; // output
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// variables
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// variables
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wire so; // sign output
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wire so; // sign output
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wire [EMSB:0] xo; // de normalized exponent output
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wire [EMSB:0] xo; // de normalized exponent output
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reg [EMSB:0] xo1; // de normalized exponent output
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reg [EMSB:0] xo1; // de normalized exponent output
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wire [FX+WX:0] mo; // mantissa output
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wire [FX:0] mo; // mantissa output
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reg [FX+WX:0] mo1; // mantissa output
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reg [FX:0] mo1; // mantissa output
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// There's an extra bit output in the mantissa to allow for three whole
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// digits which the normalizer uses.
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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// operands sign,exponent,mantissa
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// operands sign,exponent,mantissa
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wire sa, sb;
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wire sa, sb;
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wire [EMSB:0] xa, xb;
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wire [EMSB:0] xa, xb;
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wire aNan, bNan, aNan1, bNan1;
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wire aNan, bNan, aNan1, bNan1;
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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fpDecompose #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecomp #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecompose #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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fpDecomp #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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// Figure out which operation is really needed an add or
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// Figure out which operation is really needed an add or
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// subtract ?
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// subtract ?
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// If the signs are the same, use the orignal op,
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// If the signs are the same, use the orignal op,
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// otherwise flip the operation
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// otherwise flip the operation
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wire [FMSB+1:0] mfs = xa_gt_xb ? fractb : fracta;
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wire [FMSB+1:0] mfs = xa_gt_xb ? fractb : fracta;
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wire [FMSB+1:0] mfs1;
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wire [FMSB+1:0] mfs1;
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// Determine the sticky bit
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// Determine the sticky bit
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wire sticky, sticky1;
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wire sticky, sticky1;
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generate
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begin
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if (WID==128)
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redor128 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==96)
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redor96 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==80)
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redor80 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==64)
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redor64 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor64 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==32)
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redor32 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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end
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endgenerate
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// register inputs to shifter and shift
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// register inputs to shifter and shift
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky), .o(sticky1) );
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky), .o(sticky1) );
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delay1 #(7) d15(.clk(clk), .ce(ce), .i(xdif), .o(xdif1) );
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delay1 #(7) d15(.clk(clk), .ce(ce), .i(xdif), .o(xdif1) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs), .o(mfs1) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs), .o(mfs1) );
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always @*
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always @*
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casex({aInf1&bInf1,aNan1,bNan1})
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casex({aInf1&bInf1,aNan1,bNan1})
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3'b1xx: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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3'b1xx: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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3'bx1x: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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3'bx1x: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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3'bxx1: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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3'bxx1: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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endcase
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endcase
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delay1 #(FX+WX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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endmodule
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module fpAddsub_tb();
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reg clk;
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wire ce = 1'b1;
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wire [2:0] rm = 3'b0;
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wire [57:0] o1,o2,o3,o4,o5,o6;
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wire [35:0] o11,o12,o13;
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wire [31:0] o21,o22,o23;
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initial begin
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clk = 1'b0;
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end
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always #10 clk = ~clk;
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fpAddsub u1 (clk, ce, rm, 1'b0, 32'h0, 32'h0, o1); // zero plus zero
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fpAddsub u2 (clk, ce, rm, 1'b1, 32'h0, 32'h0, o2); // zero minus zero
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fpAddsub u3 (clk, ce, rm, 1'b0, 32'h3F000000, 32'h3F000000, o3); // .5 + .5
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fpAddsub u4 (clk, ce, rm, 1'b0, 32'h43520000, 32'h41700000, o4); // 210+15
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fpAddsub u5 (clk, ce, rm, 1'b1, 32'hC3520000, 32'hC1700000, o5); // -210- -15
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fpNormalize u11 (clk, ce, 1'b0, o3, o11);
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fpNormalize u12 (clk, ce, 1'b0, o4, o12);
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fpNormalize u13 (clk, ce, 1'b0, o5, o13);
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fpRound u21 (3'd1, o11, o21); // zero for zero
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fpRound u22 (3'd1, o12, o22); //
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fpRound u23 (3'd1, o13, o23); //
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endmodule
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endmodule
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