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Line 341... |
vtdl #(1) dso6(.clk(clk), .ce(ce), .a(4'd5), .d(so4), .q(so));
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vtdl #(1) dso6(.clk(clk), .ce(ce), .a(4'd5), .d(so4), .q(so));
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vtdl #(.WID(EMSB+1)) dxo6(.clk(clk), .ce(ce), .a(4'd1), .d(xo8), .q(xo));
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vtdl #(.WID(EMSB+1)) dxo6(.clk(clk), .ce(ce), .a(4'd1), .d(xo8), .q(xo));
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez({xinf9,anbInf9,aNan9,bNan9})
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casez({anbInf9,aNan9,bNan9,xinf9})
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4'b1???: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero
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4'b1???: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b01??: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b01??: mo <= {1'b0,fracta9[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo <= {1'b0,fracta9[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo <= {1'b0,fractb9[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo <= {1'b0,fractb9[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero
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default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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endcase
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endcase
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endmodule
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endmodule
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