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Line 31... |
//+-inf * +-inf = -+inf (this is handled by exOver)
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//+-inf * +-inf = -+inf (this is handled by exOver)
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//+-inf * 0 = QNaN
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//+-inf * 0 = QNaN
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//+-0 / +-0 = QNaN
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//+-0 / +-0 = QNaN
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// ============================================================================
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// ============================================================================
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module fpDiv(clk, ce, ld, a, b, o, done, sign_exe, overflow, underflow);
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`include "fp_defines.v"
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module fpDiv(clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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parameter WID = 128;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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| Line 57... |
Line 59... |
WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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localparam FADD = WID==128 ? 9 :
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WID==96 ? 9 :
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WID==80 ? 9 :
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WID==64 ? 13 :
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WID==52 ? 9 :
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WID==48 ? 10 :
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WID==44 ? 9 :
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WID==42 ? 11 :
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WID==40 ? 8 :
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WID==32 ? 10 :
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WID==24 ? 9 : 11;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input clk;
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input clk4x;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input [MSB:0] a, b;
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input [MSB:0] a, b;
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output [EX:0] o;
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output [EX:0] o;
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output done;
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output done;
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output sign_exe;
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output sign_exe;
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output overflow;
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output overflow;
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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// variables
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// variables
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wire [EMSB+2:0] ex1; // sum of exponents
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wire [EMSB+2:0] ex1; // sum of exponents
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wire [(FMSB+9)*2-1:0] divo;
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wire [(FMSB+FADD)*2-1:0] divo;
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// Operands
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// Operands
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wire sa, sb; // sign bit
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wire sa, sb; // sign bit
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wire [EMSB:0] xa, xb; // exponent bits
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wire [EMSB:0] xa, xb; // exponent bits
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta, fractb;
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| Line 119... |
Line 135... |
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// Compute the exponent.
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// Compute the exponent.
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// - correct the exponent for denormalized operands
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// - correct the exponent for denormalized operands
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// - adjust the difference by the bias (add 127)
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// - adjust the difference by the bias (add 127)
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// - also factor in the different decimal position for division
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// - also factor in the different decimal position for division
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + 9 - lzcnt;
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + (FADD-1) - lzcnt;
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// check for exponent underflow/overflow
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// check for exponent underflow/overflow
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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// Perform divide
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// Perform divide
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// could take either 1 or 16 clock cycles
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// Divider width must be a multiple of four
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fpdivr8 #(FMSB+9,2) u2 (.clk(clk), .ld(ld), .a({fracta,7'b0}), .b({fractb,7'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
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// determine when a NaN is output
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// determine when a NaN is output
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wire qNaNOut = (az&bz)|(aInf&bInf);
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wire qNaNOut = (az&bz)|(aInf&bInf);
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wire [(FMSB+9)*2-1:0] divo1 = divo[(FMSB+9)*2-1:0] << (lzcnt-2);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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if (done1) begin
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if (done1) begin
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casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
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casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
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5'b0001?: xo = infXp; // overflow
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5'b0001?: xo = infXp; // overflow
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5'b00001: xo = 0; // underflow
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5'b00001: xo = 0; // underflow
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default: xo = ex1; // normal or underflow: passthru neg. exp. for normalization
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default: xo = ex1; // normal or underflow: passthru neg. exp. for normalization
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endcase
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endcase
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casez({aNan,bNan,qNaNOut,bInf,bz,over})
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casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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6'b1?????: mo = {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
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8'b1???????: mo = {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
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6'b01????: mo = {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
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8'b01??????: mo = {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
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6'b001???: mo = {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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8'b001?????: mo = {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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6'b0001??: mo = 0; // div by inf
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8'b0001????: mo = 0; // div by inf
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6'b00001?: mo = 0; // div by zero
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8'b00001???: mo = 0; // div by zero
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6'b000001: mo = 0; // Inf exponent
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8'b000001??: mo = 0; // Inf exponent
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default: mo = divo1[(FMSB+9)*2-1:14]; // plain div
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8'b0000001?: mo = {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}}; // infinity / infinity
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8'b00000001: mo = {1'b1,qNaN|`QZEROZERO,{FMSB+1{1'b0}}}; // zero / zero
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default: mo = divo1[(FMSB+FADD)*2-1:(FADD-2)*2-2]; // plain div
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endcase
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endcase
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so = sa ^ sb;
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so = sa ^ sb;
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sign_exe = sa & sb;
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sign_exe = sa & sb;
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overflow = over;
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overflow = over;
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| Line 166... |
Line 184... |
end
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end
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end
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end
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endmodule
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endmodule
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module fpDivnr(clk, ce, ld, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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module fpDivnr(clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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parameter WID=32;
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parameter WID=32;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==80 ? 14 :
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| Line 195... |
Line 213... |
WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input clk;
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input clk4x;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input [MSB:0] a, b;
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input [MSB:0] a, b;
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output [MSB:0] o;
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output [MSB:0] o;
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input [2:0] rm;
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input [2:0] rm;
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output sign_exe;
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output sign_exe;
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output done;
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output done;
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| Line 211... |
Line 231... |
wire [EX:0] o1;
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wire [EX:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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wire done1;
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wire done1;
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fpDiv #(WID) u1 (clk, ce, ld, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpDiv #(WID) u1 (clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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