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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpDiv.v
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// fpDiv.v
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Line 32... |
//+-inf * 0 = QNaN
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//+-inf * 0 = QNaN
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//+-0 / +-0 = QNaN
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//+-0 / +-0 = QNaN
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// ============================================================================
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// ============================================================================
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`include "fp_defines.v"
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`include "fp_defines.v"
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`define GOLDSCHMIDT 1'b1
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//`define GOLDSCHMIDT 1'b1
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module fpDiv(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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parameter WID = 128;
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parameter WID = 128;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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localparam FADD = WID==128 ? 9 :
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localparam FADD = WID==128 ? 9 :
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WID==96 ? 9 :
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WID==96 ? 9 :
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WID==84 ? 9 :
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WID==80 ? 9 :
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WID==80 ? 9 :
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WID==64 ? 13 :
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WID==64 ? 13 :
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WID==52 ? 9 :
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WID==52 ? 9 :
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WID==48 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 9 :
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WID==44 ? 9 :
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WID==42 ? 11 :
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WID==42 ? 11 :
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WID==40 ? 8 :
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WID==40 ? 8 :
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WID==32 ? 10 :
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WID==32 ? 10 :
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WID==24 ? 9 : 11;
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WID==24 ? 9 : 11;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input rst;
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input rst;
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input clk;
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input clk;
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input clk4x;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input op;
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input [MSB:0] a, b;
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input [MSB:0] a, b;
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output [EX:0] o;
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output [EX:0] o;
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Line 131... |
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// Perform divide
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// Perform divide
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// Divider width must be a multiple of four
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// Divider width must be a multiple of four
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`ifndef GOLDSCHMIDT
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`ifndef GOLDSCHMIDT
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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`else
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`else
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DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+6)*2+1:0] divo1 =
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wire [(FMSB+6)*2+1:0] divo1 =
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Line 194... |
end
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end
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end
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end
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endmodule
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endmodule
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module fpDivnr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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module fpDivnr(rst, clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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parameter WID=32;
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parameter WID=32;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input rst;
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input rst;
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input clk;
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input clk;
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input clk4x;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input op;
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input [MSB:0] a, b;
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input [MSB:0] a, b;
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output [MSB:0] o;
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output [MSB:0] o;
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Line 218... |
wire [EX:0] o1;
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wire [EX:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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wire done1;
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wire done1;
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fpDiv #(WID) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpDiv #(WID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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