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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Stratford
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpDiv.v
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// - floating point divider
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// - parameterized width
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// - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// fpDiv.v
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// Floating Point Multiplier / Divider
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// - floating point divider
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// - parameterized width
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// - IEEE 754 representation
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//
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// Floating Point Divider
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//
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//
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// Properties:
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// Properties:
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//+-inf * +-inf = -+inf (this is handled by exOver)
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//+-inf * 0 = QNaN
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// +-0 / +-0 = QNaN
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// +-0 / +-0 = QNaN
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//
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// ============================================================================
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// ============================================================================
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//
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module fpDiv(clk, ce, ld, a, b, o, done, sign_exe, overflow, underflow);
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module fpDiv(clk, ce, ld, a, b, o, done, sign_exe, overflow, underflow);
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parameter WID = 32;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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localparam WX = 3;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+1)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + WX + EMSB + 1;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [MSB:0] a, b;
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input [MSB:0] a, b;
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output [EX+1:0] o;
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output [EX:0] o;
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output done;
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output done;
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output sign_exe;
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output sign_exe;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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reg overflow;
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reg overflow;
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reg underflow;
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reg underflow;
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reg so;
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reg so;
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reg [EMSB:0] xo;
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reg [EMSB:0] xo;
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reg [FX+WX:0] mo;
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reg [FX:0] mo;
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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// constants
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// constants
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wire [EMSB:0] infXp = {EMSB+1{1'b1}}; // infinite / NaN - all ones
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wire [EMSB:0] infXp = {EMSB+1{1'b1}}; // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// The following is the value for an exponent of zero, with the offset
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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// variables
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// variables
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wire [EMSB+2:0] ex1; // sum of exponents
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wire [EMSB+2:0] ex1; // sum of exponents
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wire [FX+WX:0] divo;
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wire [FX:0] divo;
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// Operands
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// Operands
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wire sa, sb; // sign bit
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wire sa, sb; // sign bit
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wire [EMSB:0] xa, xb; // exponent bits
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wire [EMSB:0] xa, xb; // exponent bits
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta, fractb;
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wire a_dn, b_dn; // a/b is denormalized
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wire a_dn, b_dn; // a/b is denormalized
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wire az, bz;
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wire az, bz;
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wire aInf, bInf;
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wire aInf, bInf;
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wire aNan,bNan;
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// - decode the input operands
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// - decode the input operands
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// - derive basic information
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// - derive basic information
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// - calculate exponent
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// - calculate exponent
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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fpDecompose #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf) );
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fpDecomp #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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fpDecompose #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf) );
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fpDecomp #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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// Compute the exponent.
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// Compute the exponent.
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// - correct the exponent for denormalized operands
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// - correct the exponent for denormalized operands
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// - adjust the difference by the bias (add 127)
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// - adjust the difference by the bias (add 127)
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// - also factor in the different decimal position for division
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// - also factor in the different decimal position for division
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + 1;
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB - 1;
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// check for exponent underflow/overflow
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// check for exponent underflow/overflow
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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// Perform divide
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// Perform divide
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// could take either 1 or 16 clock cycles
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// could take either 1 or 16 clock cycles
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fpdivr2 #(FMSB+2) u2 (.clk(clk), .ld(ld), .a(fracta), .b(fractb), .q(divo[(FMSB+1)*2-1:0]), .r(), .done(done));
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fpdivr8 #(FMSB+2,2) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta}), .b({3'b0,fractb}), .q(divo), .r(), .done(done));
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assign divo[FX+WX:(FMSB+1)*2] = 0;
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// determine when a NaN is output
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// determine when a NaN is output
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wire qNaNOut = (az&bz)|(aInf&bInf);
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wire qNaNOut = (az&bz)|(aInf&bInf);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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if (done) begin
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if (done) begin
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casex({qNaNOut,bInf,bz})
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casex({qNaNOut|aNan|bNan,bInf,bz})
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3'b1xx: xo = infXp; // NaN exponent value
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3'b1xx: xo = infXp; // NaN exponent value
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3'bx1x: xo = 0; // divide by inf
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3'bx1x: xo = 0; // divide by inf
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3'bxx1: xo = infXp; // divide by zero
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3'bxx1: xo = infXp; // divide by zero
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default: xo = ex1; // normal or underflow: passthru neg. exp. for normalization
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default: xo = ex1; // normal or underflow: passthru neg. exp. for normalization
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endcase
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endcase
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casex({qNaNOut,bInf,bz})
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casex({aNan,bNan,qNaNOut,bInf,bz})
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3'b1xx: mo = {1'b0,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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5'b1xxxx: mo = {1'b0,a[FMSB:0],{FMSB+1{1'b0}}};
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3'bx1x: mo = 0; // div by inf
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5'bx1xxx: mo = {1'b0,b[FMSB:0],{FMSB+1{1'b0}}};
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3'bxx1: mo = 0; // div by zero
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5'bxx1xx: mo = {1'b0,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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5'bxxx1x: mo = 0; // div by inf
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5'bxxxx1: mo = 0; // div by zero
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default: mo = divo; // plain div
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default: mo = divo; // plain div
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endcase
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endcase
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so = sa ^ sb;
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so = sa ^ sb;
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sign_exe = sa & sb;
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sign_exe = sa & sb;
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end
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end
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end
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end
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endmodule
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endmodule
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module fpDiv_tb();
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reg clk;
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reg ld;
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wire ce = 1'b1;
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wire sgnx1,sgnx2,sgnx3,sgnx4,sgnx5,sgnx6;
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wire inf1,inf2,inf3,inf4,inf5,inf6;
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wire of1,of2,of3,of4,of5,of6;
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wire uf1,uf2,uf3,uf4,uf5,uf6;
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wire [57:0] o1,o2,o3,o4,o5,o6;
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wire [35:0] o11,o12,o13;
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wire [31:0] o21,o22,o23;
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wire done0,done1,done2,done3,done4,done5,done6;
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initial begin
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clk = 0;
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ld = 0;
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#20 ld = 1;
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#40 ld = 0;
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end
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always #10 clk <= ~clk;
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fpDiv u1 (.clk(clk), .ce(1'b1), .ld(ld), .a(0), .b(0), .o(o1), .done(done1), .sign_exe(sgnx1), .overflow(of1), .underflow(uf1));
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fpDiv u2 (.clk(clk), .ce(1'b1), .ld(ld), .a(0), .b(0), .o(o2), .done(done2), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
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// 10/10
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fpDiv u3 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'h41200000), .b(32'h41200000), .done(done3), .o(o3), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
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// 21/-17
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fpDiv u4 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'h41a80000), .b(32'hc1880000), .done(done4), .o(o4), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
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// -17/-15
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fpDiv u5 (.clk(clk), .ce(1'b1), .ld(ld), .a(32'hc1880000), .b(32'hc1700000), .done(done5), .o(o5), .sign_exe(sgnx2), .overflow(of2), .underflow(uf2));
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fpNormalize u11 (clk, ce, 1'b0, o3, o11);
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fpNormalize u12 (clk, ce, 1'b0, o4, o12);
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fpNormalize u13 (clk, ce, 1'b0, o5, o13);
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fpRound u21 (3'd1, o11, o21); // zero for zero
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fpRound u22 (3'd1, o12, o22); //
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fpRound u23 (3'd1, o13, o23); //
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endmodule
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