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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDiv_tb.v] - Diff between revs 10 and 11

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Rev 10	Rev 11
Line 38...	Line 38...
`reg rst;`	`reg rst;`
`reg clk;`	`reg clk;`
`reg [12:0] adr;`	`reg [12:0] adr;`
`reg [95:0] mem [0:8191];`	`reg [95:0] mem [0:8191];`
`reg [95:0] memo [0:9000];`	`reg [95:0] memo [0:9000];`
	`reg [191:0] memd [0:8191];`
	`reg [191:0] memdo [0:9000];`
`reg [31:0] a,b,a6,b6;`	`reg [31:0] a,b,a6,b6;`
	`reg [63:0] ad,bd;`
`wire [31:0] a5,b5;`	`wire [31:0] a5,b5;`
`wire [31:0] o;`	`wire [31:0] o;`
	`wire [63:0] od;`
`reg ld;`	`reg ld;`
`wire done;`	`wire done;`
`reg [3:0] state;`	`reg [3:0] state;`

`initial begin`	`initial begin`
`rst = 1'b0;`	`rst = 1'b0;`
`clk = 1'b0;`	`clk = 1'b0;`
`adr = 0;`	`adr = 0;`
`$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tv.txt", mem);`	`$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tv.txt", mem);`
	`$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvd.txt", memd);`
`#20 rst = 1;`	`#20 rst = 1;`
`#50 rst = 0;`	`#50 rst = 0;`
`end`	`end`

`always #5`	`always #5`
Line 70...	Line 75...
`case(state)`	`case(state)`
`4'd1:`	`4'd1:`
`begin`	`begin`
`a <= mem[adr][31: 0];`	`a <= mem[adr][31: 0];`
`b <= mem[adr][63:32];`	`b <= mem[adr][63:32];`
	`ad <= memd[adr][63:0];`
	`bd <= memd[adr][127:64];`
`ld <= 1'b1;`	`ld <= 1'b1;`
`state <= 2;`	`state <= 2;`
`end`	`end`
`4'd2:`	`4'd2:`
`if (done) begin`	`if (done) begin`
`memo[adr] <= {o,b,a};`	`memo[adr] <= {o,b,a};`
	`memdo[adr] <= {od,bd,ad};`
`adr <= adr + 1;`	`adr <= adr + 1;`
`if (adr==8191) begin`	`if (adr==8191) begin`
`$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvo.txt", memo);`	`$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvo.txt", memo);`
	`$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvdo.txt", memdo);`
`$finish;`	`$finish;`
`end`	`end`
`state <= 3;`	`state <= 3;`
`end`	`end`
`4'd3: state <= 4;`	`4'd3: state <= 4;`
`4'd4: state <= 5;`	`4'd4: state <= 5;`
`4'd5: state <= 1;`	`4'd5: state <= 1;`
`endcase`	`endcase`
`end`	`end`

`fpDivnr #(32) u1 (clk, 1'b1, ld, a, b, o, 3'b000, done);//, sign_exe, inf, overflow, underflow);`	`fpDivnr #(32) u1 (clk, 1'b1, ld, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);`
	`fpDivnr #(64) u2 (clk, 1'b1, ld, ad, bd, od, 3'b000, done);//, sign_exe, inf, overflow, underflow);`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDiv_tb.v] - Diff between revs 10 and 11